A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $Sigma Delta$ Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.     

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $SigmaDelta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.     

A 2.5-V 14-bit, 180-mW Cascaded Σ∆ ADC for ADSL2+ Application

This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm² active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.     

Adaptive Blocker Rejection Continuous-Time $Sigma Delta $ ADC for Mobile WiMAX Applications

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm² silicon area.     

Reconfigurable ADCs enable smart radios for 4G wireless connectivity

A reconfigurable ADC based on a 2-2 modified cascaded /spl Sigma//spl Delta/ modulator designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver has been presented. Employing the second-order feedforward /spl Sigma//spl Delta/ modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth is achieved. The P-DWA technique is applied in the first feedback 4-b DAC to eliminate the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes.     

A low-power highly digitized receiver for 2.4-GHz-band GFSK applications

This paper describes the design and measurement results of a low-power highly digitized receiver for Gaussian frequency-shift keying modulated input signals at 2.4 GHz. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous SigmaDelta analog-to-digital converter (ADC). This leads to a linear receive chain without limiters. A fifth-order poly-phase loop filter is used in the complex SigmaDelta ADC. The digital block performs filtering and demodulation. Channel filtering is combined with matched filtering and the suppression of noise resulting from the SigmaDelta ADC. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-mum CMOS process and measures 3.5 mm². The only external components are an antenna filter and a crystal. The power consumption is only 32 mW in the continuous mode, which is at least a factor of two lower than state-of-the-art CMOS receivers     

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm²     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.     

Analytical Settling Noise Models of Single-Loop Sigma–Delta ADCs

Switched-capacitor integrators are the basic building components for sigma-delta (SigmaDelta) modulators, and their incomplete charge transfer (settling problem) constitutes one of the dominant error sources in SigmaDelta modulators. Due to the complexity of the settling problem, analytic models for related noises are nonexistent. In this brief, closed forms of settling error models are obtained and represented as functions of SigmaDelta modulator system parameters. Both behavioral simulations and transistor-level circuit simulations are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate.     

A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

A 0.7-V 870-$mu$ W Digital-Audio CMOS Sigma-Delta Modulator

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta $(SigmaDelta)$ modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-$mu{hbox {m}}$ CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870$ muhbox{W}$ of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.      

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta–sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.     

Efficient Multibit Quantization in Continuous-Time Σ∆ Modulators

A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

Cascade SD modulator for low-voltage wideband applications

A new cascade SigmaDelta modulator architecture with unity signal transfer function is presented which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.