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1.
Fang-Ting Chou Chia-Min Chen Chung-Chih Hung 《Analog Integrated Circuits and Signal Processing》2014,79(2):277-289
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply. 相似文献
2.
O'Sullivan K. Gorman C. Hennessy M. Callaghan V. 《Solid-State Circuits, IEEE Journal of》2004,39(7):1064-1072
A 12-bit 320-MSample/s current-steering D/A converter in 0.18-/spl mu/m CMOS is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), a large degree of segmentation has been used, with the seven most significant bits (MSBs) being implemented as equally weighted current sources. A "design-for-layout" approach has allowed this to be done in an area of just 0.44 mm/sup 2/. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch architecture. Differential nonlinearity of /spl plusmn/0.3 LSB and integral nonlinearity of /spl plusmn/0.4 LSB have been measured. Low-frequency SFDR of 95 dB has been achieved, while SFDR at 320 MS/s remains above 70 and 60 dB for input frequencies up to 10 and 60 MHz, respectively. The converter consumes a total of 82 mW from 1.8-V and 3.3-V supplies. The validity of the techniques used has been demonstrated by fabricating the converter in two separate 0.18-/spl mu/m processes with similar results measured for both. 相似文献
3.
基于新型的低压与温度成正比(PTAT)基准源和PMOS衬底驱动低压运算放大器技术,采用分段温度计译码结构设计了一种1.5V8位100MS/s电流舵D/A转换器,工艺为TSMC0.25μm2P5MCMOS。当采样频率为100MHz,输出频率为20MHz时,SFDR为69.5dB,D/A转换器的微分非线性误差(DNL)和积分非线性误差(INL)的典型值分别为0.32LSB和0.52LSB。整个D/A转换器的版图面积为0.75mm×0.85mm,非常适合SOC的嵌入式应用。 相似文献
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5.
Peiman Aliparast Nasser Nasirzadeh 《Analog Integrated Circuits and Signal Processing》2009,60(3):195-204
In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation
(90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher
performance is achieved using a novel 3-D thermometer decoding method which reduces the area, power consumption, and the number
of control signals of the digital section. Simulation results show that the spurious-free-dynamic-range (SFDR) in Nyquist
rate is better than 65 dB for sampling frequency up to 1.2-GSample/s. The analog voltage supply is 3.3 V while the digital
part of the chip operates at only 2.4 V. Total power consumption in Nyquist rate measurement is 149 mW. The chip has been
processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.97 mm2. 相似文献
6.
7.
实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。 相似文献
8.
《IEEE transactions on circuits and systems. I, Regular papers》2008,55(9):2459-2468
9.
《半导体学报》2010,31(2)
This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious flee dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3. 1 × 2.1 mm~2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply. 相似文献
10.
采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器(ADC)。为了减小失真和降低功耗,该ADC利用余量增益放大电路(MDAC)内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。 相似文献
11.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(2):137-141
12.
《半导体学报》2010,31(2)
A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process. 相似文献
13.
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter 总被引:3,自引:0,他引:3
van den Bosch A. Borremans M.A.F. Steyaert M.S.J. Sansen W. 《Solid-State Circuits, IEEE Journal of》2001,36(3):315-324
In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm2 相似文献
14.
This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply. 相似文献
15.
In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V. 相似文献
16.
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V. 相似文献
17.
Peiman Aliparast Ziaadin Daei Koozehkanany Jafar Sobhi 《Analog Integrated Circuits and Signal Processing》2011,68(3):315-328
In this paper a 12-bit Nyquist current-steering digital-to-analog converter (DAC) is implemented using TSMC 0.35 μm standard
CMOS process technology. The proposed DAC is an essential part in baseband section of wireless transmitter circuits. Using
oversampling ratio (OSR) for it leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%)
has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance
is achieved using a new 3D thermometer decoding method which reduces the area, power consumption and the number of control
signals of the digital section. Using two digital channels in parallel, helps reach 1 GHz sampling frequency. Simulations
indicate that the DAC has an accuracy better than 10.7-bit for upcoming higher data rate standards (IEEE 802.16 and 802.11n),
and a spurious-free-dynamic-range (SFDR) higher than 64 dB in whole Nyquist frequency band. The post layout four corner Monte-Carlo
simulated INL is better than 0.74 LSB while simulated DNL is better than 0.49 LSB. The analog voltage supply is 3.3 V while
the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. Active
area of chip is 1.37 mm2. 相似文献
18.
In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture
and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and
a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive
networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid
DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that
the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better
than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is
higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit
resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with
good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable
modems etc. 相似文献
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20.
This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency. 相似文献