A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

A 6.75 ns 16×16 bit multiplier in single-level-metal CMOStechnology

A 16×16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 μm devices     

A low-power 16×16-b parallel multiplier utilizingpass-transistor logic

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz     

A high-speed LSI GaAs 8/spl times/8 bit parallel multiplier

Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.     

16*16 bit parallel multiplier based on 6 K gate array with 0.3 mu m AlGaAs/GaAs quantum well transistors

The design and performance of a 16*16 bit parallel multiplier based on a 6 K gate array will be presented. This LSI semicustom IC demonstrates the high potential of the authors' AlGaAs/GaAs quantum well FETs with a gate length of 0.3 mu m. The best multiplication time measured was 7.2 ns.<>     

Suggestion for an i.c. fast parallel multiplier

A general method for handling partial products in a parallel multiplier is proposed. It leads to a network of AND gates and full adders, availables as i.c.s which can have an operation time of less than 10 ns per bit of the result.     

适用于VLSI的一种并行乘法器结构

本文给出了二进制补码和无符号乘法器的通用表达式。对VLSI乘法器的结构进行了讨论。     

A fast final adder for a 54-bit parallel multiplier for DSP application

A novel redundant binary-to-natural binary converter circuit is proposed which is used in the final addition stage of parallel multipliers. Use of this circuit in the final adder stage proves to be 17% faster than carry-look-ahead implementation. We used this algorithm in such a way that no redundant binary adder is required in compressing partial product rows. Only the natural 4:2 compressor circuits are used.     

HDTV RS码编译码器中的论文对偶基比特并行乘法器

重点介绍了一种适合ＨＤＴＶ的ＲＳ码编译码器乘法器：对偶基比特并行乘法器的算法和实现方案。根据有限域ＧＦ（ｐｍ）中的有关定义和定理导出了对偶基比特并行乘法器的算法；给出了详细的实现电路并举例说明了其应用；简要介绍了其在ＨＤＴＶ的ＲＳ码编译码器中的应用，并和“查表法”实现的乘法器作了比较。说明了对偶基比特并行乘法器在硬件规模上的优越性。     

基于16位定点DSP的并行乘法器的设计

设计了一种用于1 6位定点DSP中的片内乘法器.该乘法器采用了改进型Booth算法,使用CSA构成的乘法器阵列,并采用跳跃进位加法器实现进位传递,该设计具有可扩展性,并提出了更高位扩展时应改进型方向.设计时综合考虑了高性能定点DSP对乘法器在面积和速度上的要求,具有极其规整的布局布线.     

A 16-bit self-testing multiplier

A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.     

Faster parallel multiplier

Realization of a parallel multiplier has been considered in a paper by Dadda [1] who has proposed various schemes to get the product using (3, 2), (2, 2) counters, and carry look-ahead adders. The complexity of the carry look-ahead adder in terms of number of two-input gates increases with the length of the adder which in effect reduces the speed. This letter presents an approach that reduces the length of carry look-ahead adder, thus increasing the computation speed with a reduction in logic complexity.     

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.     

High-speed NMOS circuits for ROM-accumulator and multiplier type digital filters

Using a standard 6 /spl mu/m NMOS silicon-gate process, circuit techniques are described for the full integration of high-speed ROM-accumulator and multiplier type digital filters. The ROM-accumulator structure is integrated using a new two-clock four-phase technique which can be used both for ROM and accumulator. An operating speed of 20 Mbits/s is measured. The circuit shows that an eighth-order filter on a 20 mm/SUP 2/ chip, dissipating only 400 mW at 10 Mbits/s is feasible. Using a 4-clock 4-phase technique a 4-bit serial-parallel multiplier is presented featuring 20 Mbits/s operation into a 15 pF load. Power dissipation is 7 mW/cell. Cell area is 0.2 mm/SUP 2/.     

光学全并行矩阵乘法

本文提出一种只用极少数成像系统就能完成的一种全并行矩阵运算器.     

On sign bit assignment for a vector multiplier

A simple sign bit assignment scheme for each SHIFT operation of a vector multiplier is presented. This new scheme is capable of determining the correct sign for a shifted sum independent of overflow conditions during each ADD operation.     

一种应用平行反馈补偿和瞬态响应增强技术的NMOS低压差电压调整器设计

本文提出了一种应用于便携式设备的,采用平行反馈补偿和瞬态响应增强技术的低压差电压调整器。平行反馈的架构引入了一个动态零点,保证环路在0A到1A的负载电流范围内具有足够的相位裕度。通过采用Class-AB结构的误差运放和快速充放电单元增强系统的瞬态响应能力。本文提出的低压差电压调整器采用0.35μm BCD工艺制造。测试结果显示,稳压器的静态电流为165μA,在1A满载情况下,压差可以达到150mV。在满负载瞬态跳变时,输出电压下掉和过冲幅度分别降低到38mV和27mV。     

N bit result integer multiplier with overflow detector

This study is designed to suggest an N bit result integer multiplier with overflow detector indicating an N bit multiplication result and overflow status with an N bit multiplier and multiplicand input. The overflow is determined by the lower N bit result of multiplication and the number of leading sign bits of the multiplier and the multiplicand     

An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling

A single-chip multiple-channel D/A converter is described. The NMOS chip contains a combination of digital and analog functions. Eight output channels with 8 bit accuracy are provided and each channel has programmable end points. The values for the data and the end points are stored in an internal RAM. Sample and-hold functions are completely on-chip. Only one multiplexed opamp is required for the analog functions. The entire control logic is incorporated in an easily testable PLA. The active chip area is 8 mm/SUP 2/. There are three power supplies (15,5,-5) with a total power dissipation of 120 mW. Updating of the eight channels occurs at a 16 kHz rate (5 MHz clock). The circuit aims at applications in microprocessor driven control systems in the industrial and consumer products field.