Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.     

Low-threshold continuous-wave 1.5-/spl mu/m GaInNAsSb lasers grown on GaAs

We present the first continuous-wave (CW) edge-emitting lasers at 1.5 /spl mu/m grown on GaAs by molecular beam epitaxy (MBE). These single quantum well (QW) devices show dramatic improvement in all areas of device performance as compared to previous reports. CW output powers as high as 140 mW (both facets) were obtained from 20 /spl mu/m /spl times/ 2450 /spl mu/m ridge-waveguide lasers possessing a threshold current density of 1.06 kA/cm/sup 2/, external quantum efficiency of 31%, and characteristic temperature T/sub 0/ of 139 K from 10/spl deg/C-60/spl deg/C. The lasing wavelength shifted 0.58 nm/K, resulting in CW laser action at 1.52 /spl mu/m at 70/spl deg/C. This is the first report of CW GaAs-based laser operation beyond 1.5 /spl mu/m. Evidence of Auger recombination and intervalence band absorption was found over the range of operation and prevented CW operation above 70/spl deg/C. Maximum CW output power was limited by insufficient thermal heatsinking; however, devices with a highly reflective (HR) coating applied to one facet produced 707 mW of pulsed output power limited by the laser driver. Similar CW output powers are expected with more sophisticated packaging and further optimization of the gain region. It is expected that such lasers will find application in next-generation optical networks as pump lasers for Raman amplifiers or doped fiber amplifiers, and could displace InP-based lasers for applications from 1.2 to 1.6 /spl mu/m.     

Low-voltage micropower super class AB CMOS OTA

Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps

A simple modification to a one-stage op-amp for operation as a class AB amplifier leads to significant slew rate and bandwidth enhancement with essentially equal silicon area and static power dissipation requirements. Experimental results of a prototype in 0.5 /spl mu/m CMOS verify SR and bandwidth enhancement factors of almost one order of magnitude.     

Micropower CMOS S&H circuit for ambient intelligence applications

A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 /spl mu/m double-poly CMOS technology. The quiescent power consumption is only 80 /spl mu/W using a dual supply voltage of /spl plusmn/1.35 V. The S&H occupies 0.075 mm/sup 2/ of silicon area.     

A high-efficiency CMOS +22-dBm linear power amplifier

Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-/spl mu/m CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.     

Low-power low-voltage differential class-AB OTAs for SC circuits

Two new differential class-AB operational transconductance amplifiers (OTAs) for SC circuits that operate with a supply voltage of less than two transistor threshold voltages are introduced. They make use of a new class-AB pseudodifferential pair to generate signal currents much larger than quiescent currents. Both OTAs have been designed to operate with a supply voltage of V/sub DD/=1.1 V, using a 0.35 /spl mu/m CMOS technology. Simulation results for a load capacitance (C/sub L/) of 1 pF show 15 MHz gain-bandwidth product with a quiescent power consumption of 10 /spl mu/W.     

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.     

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.     

Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers

Novel adaptive biasing techniques, suited for low-voltage operation, are presented. They provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied. Measurement results of an OTA using these techniques and fabricated in a 0.5 /spl mu/m CMOS technology show a slew rate of more than 40 V//spl mu/s for an 80 pF load capacitance and a static power consumption of only 140 /spl mu/W.     

Large-signal performance of deep submicrometer AlGaN/AlN/GaNHEMTs with a field-modulating plate

This is the first time that the microwave performance of a 0.1-/spl mu/m gate in a silicon nitride window opening, with a field-modulating plate on an AlGaN/AlN/GaN heterojunction structure, is reported. The material structure was grown by organometallic vapor phase epitaxy on SiC substrates with an averaged channel sheet resistance of 313.5 ohms/square. Approximately 80-nm-thick plasma-enhanced chemical vapor deposition silicon nitride is used as the dielectric between gate metal extension and semiconductor surface. Transistors of a total gate width of 250 /spl mu/m and a 0.1 /spl mu/m gate footprint, with a 0.36 /spl mu/m long overhang on top of the silicon nitride, can be operated at a drain bias of 40-V high. Output power density of 9.5 W/mm, with 36% power-added efficiency in class AB regime, was demonstrated at 10 GHz in a continuous wave power measurement.     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.     

2.2 GHz all-n-p-n second-generation controlled conveyor in pseudoclass AB using 0.8-/spl mu/m BiCMOS technology

A new second-generation controlled current conveyor (CCCII), implemented using a 0.8-/spl mu/m Si-BiCMOS process, and operating in pseudoclass AB, is presented. It uses only n-p-n transistors to convey the signal, and CMOS transistors to bias the circuit. The expressions for the intrinsic resistance R/sub X/ and class of operation are derived. The performance of the circuit in voltage and current follower modes is described. Its electrical characteristics (voltage and current transfers, parasitic impedances) are compared with some other recent CCCII implementations. At a bias current of 550 /spl mu/A, and supplied under /spl plusmn/2.2 V, the conveyor exhibits R/sub X/ value as low as 2.2 /spl Omega/. Passbands of dc to 2.2 GHz are exhibited for both voltage and current transfers.     

Fabrication and characteristics of GaP-AlGaP tapered waveguide semiconductor Raman amplifiers

We have fabricated GaP-AlGaP tapered waveguide semiconductor Raman amplifiers, and analyzed the effect of tapering in pulse-pumped high-gain operation. The finesse measurement and 80-ps pulse pumped Raman amplification experiment were performed. Although the tapering has caused additional optical loss, the highest gain of 23 dB has been obtained for a tapered waveguide with input facet of 6.0 /spl mu/m/sup 2/ and back facet of 2.9 /spl mu/m/sup 2/ at averaged input power of 170 mW (peak power 26 W). It is shown that the optical loss of the pump light is more severe than the linear optical loss of the signal light when the gain is higher than 20 dB.     

A low-power low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.     

A high-speed 64K CMOS RAM with bipolar sense amplifiers

A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mW active power and 100 nW standby power. A CMOS six-transistor memory cell is used. The cell size is 18/spl times/20 /spl mu/m, and the chip size is 5.95/spl times/6.84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing, thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the word line delay, the MoSi layer, which has 5 /spl Omega//sheet resistivity, was used for the gate material. The n-well CMOS process is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics. The n-p-n transistor has a 2-GHz cutoff frequency at 1 mA collector current.     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.