An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

Output characteristics of short-channel field-effect transistors

A recent model for hot-electron MOS transistors [4], [5] is generalized for short-channel field-effect transistors. It is based on six to seven parameters for the carrier mobility under the influence of transverse and Iongitudinal electric fields, for the threshold voltage and its dependence on drain bias, and for a finite longitudinal field at pinch-off. Such important features of short-channel FET's like reduced available current and voltage gain are well represented, where the latter turns up as important limiting factor in submicron devices. Effects of zero-field mobility, impurities, and device geometry are stated explicitly. The results are confirmed by measured data on 0.9-µm silicon gate MOSFET's.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

An analytical drain current model for submicrometer and deepsubmicrometer MOSFET's

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFET's

A new two-dimensional device simulator is developed to investigate the effects of velocity overshoot on Si MOSFET's. An electron temperature-dependent mobility model, in which mobility is determined as a function of electron-gas temperature, is used in the simulator. Marked velocity overshoot occurs in the vicinity of the drain edge of MOSFET's and makes the potential barrier height at the source edge lower for ultrashort-channel MOSFET's. Therefore, velocity overshoot effects appear not only as degradation of electron transit time but also as increased drain current as compared with the case in which drift velocity does not overshoot. The increase in drain current depends strongly upon low-field mobility and bias conditions and appears for channel lengths shorter than 1000 nm. When low-field mobility is higher than 500 cm²/V. s and channel length is 100 nm, the increase in drain current is more than 1.5 times for bias conditions of strong inversion and a lateral electric field of more than 10⁵V/cm in the vicinity of the drain edge.     

New device degradation due to `cold' carriers created byband-to-band tunneling

Device degradation caused by so-called `cold' carriers due to band-to-band tunneling in a MOS drain region is studied. The cold carriers acquire energy from the electric field in the drain region and surmount the Si-SiO₂ barrier. In an n-channel device, injected holes cause a decrease in the tunnel current and a negative MOS threshold-voltage shift opposite to that observed in hot-carrier degradation previously reported. A simple analytical model is presented. This model agrees well with the experimental data in both n- and p-channel devices     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10^-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

A new approach to determine the drain-and-source series resistanceof LDD MOSFET's

A method for determining the intrinsic drain-and-source series resistance and the effective channel length of LDD MOSFET's is proposed. The method is based on the experimentally measured device I-V characteristics and a new parameter extraction procedure. A consistent set of the effective channel length and the gate-voltage-dependent drain-and-source series resistance was thus determined. The comparison between the measured and experimental drain current characteristics shows excellent agreement using the present model values     

Impact ionization current in MOS devices

An impact ionization current flows in the substrate of an MOS device which is operated in the saturation region. This current results from hole-electron pairs created by impact ionization in the drain depletion region. This paper utilizes the transverse electric field across the depletion region and the probability of creating a hole-electron pair as a function of this field to calculate substrate current which is then compared with measured data.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

An empirical model for device degradation due to hot-carrier injection

An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a Vthshift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.     

MOSFET's on Au-diffused high-resistivity Si substrates

Si MOSFET's on Au-diffused high-resistivity substrates were fabricated and their electrical properties were investigated. At 80 K, the current leakage between the source and drain of both n- and p-channel devices decreased below 10^-10A, and the devices exhibited normally-off behaviors. Au concentrations (N) in Si substrates as a function of diffusion temperature Tdiffwas determined from the change in the threshold voltage.Nversus Tdiffthus obtained is in fairly good agreement with that obtained by other methods. Dependence of effective mobility on Tdiffwas investigated in the form of a MOS device. The effective mobility decreased with increasing Tdiff, and it became clear that the diffusion temperature must be lower than about 700°C to obtain semi-insulating substrates with reasonably high carrier mobility. A C-MOS inverter was fabricated using an Au-diffused Si substrate, where no isolation wells were needed, in operation at low temperatures.