An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 μm CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin     

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.     

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. R_onmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated R_onmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

A 5+ 1-lane 3–10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology

In this paper, a 3–10 Gbps source synchronous receiver macro in 65 nm CMOS technology is presented. The receiver consists of 5 data lanes and a forwarded clock lane, featuring a wide frequency operating range. In the forwarded clock lane, a duty cycle correction loop is implemented to cancel the clock duty cycle distortion. A DLL with a wide locking range from 1 to 6 GHz is designed to generate quadrature clocks. Time-averaging is used to improve clock quality. A linear equalizer with level shift and offset cancellation is implemented in the DC coupled data lane, which compensates the channel loss and shifts the data DC level to accommodate NMOS input amplifier to save power. The phase interpolator based CDR design is optimized and a ring counter based phase interpolator controller is implemented to realize the phase rotation. The power consumption for the 5+ 1 lane RX PHY core running at 10 Gbps is 175 mW or 3.5 mW/Gbps under 1.2 V power supply, achieving a BER < 1e-12.     

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques

Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext.     

高性能同步数字传输/光纤网络芯片组

文中介绍了一种2．5Gbps同步数字传输／光纤网络（SDH／SONET）芯片组。发送器由MAX3890（合路器、时钟发生器）和MAX3867（激光驱动器）组成,总随机抖动仅为3．4psRMS,MAX3890可提供2．5Gbps时钟给MAX3867的输入锁定,用于数据信号的再定时,使MAX3867成为仅有的系统性抖动源,典型的系统性抖动≤50psRMS。接收器由MAX3866（TIA）、MAX3875（时种及数据恢复）和MAX3885（分路器）组成,总随机抖动仅4．6psRMS系统性抖动约为20psRMS。该芯片组对于ITU／Bellcore关于2．5Gbps SDH/SONET抖动规范有显著的设计裕量。     

2Gbps GaAs单片4bit数模转换器的设计与实现

详述了单片超高速2G bps G aA s 4b it数模转换器(DAC)的设计、制造及测试。在南京电子器件研究所标准76 mm G aA s工艺线采用0.5μm全离子注入M ESFET工艺完成流片。芯入输入输出阻抗实现在片50Ω匹配。4 b it DAC的微分非线性(DN L)为±0.22最低有效位(LSB),积分非线性(IN L)为±0.45LSB,达到5.2 b it的转换精度。该单片电路提供差分互补输出,长周期输出特性无漂移。其最高转换速率可达2 G bps,建立时间小于250 ps,电路核心部分功耗为110 mW。     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s     

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 μm E/D MESFET process     

A monolithic 156 Mb/s clock and data recovery PLL circuit using thesample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2²³-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor     

A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process.     

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX     

A multigigahertz clocking scheme for the Pentium(R) 4microprocessor

Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies ⩾2 GHz for the core and ⩾4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle     

A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM

A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V.     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

Multi-Rate SerDes Transceiver for IEEE 1394b Applications

This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2 including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.     

Study of a SiGe-HBT-based 1：2 demultiplexer IC up to 100 Gb/s rate

An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis sho...