Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $hbox{HfO}_{bf 2}$ Gate Stacks

A model is established to describe the temperature dependence of the electron tunneling current through HfO₂ gate stacks based on analyzing the coupling between the longitudinal and transverse components of electron thermal energy caused by the difference of the effective electron mass between the HfO₂ gate stacks and silicon. By analyzing the three-dimensional Schrodinger equation for a MOS structure with HfO₂ gate stacks, a reduction in the barrier height is resulted from the large effective electron mass mismatch between the gate oxide and the gate (substrate). The calculated electron tunneling currents agree well with the experimental data over a wide temperature range. This coupling model can explain the temperature dependence of the electron tunneling current through HfO₂ gate stacks very well. The numerical results also demonstrate that the temperature dependence of the electron tunneling current strongly depends on the effective electron mass of HfO₂. This temperature sensitivity of the electron tunneling current can be proposed as a novel method to determine the effective electron mass of the gate oxide.     

Current transport in metal/hafnium oxide/silicon structure

Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for metal/HfO₂/Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: i) HfO₂/Si conduction band offset (or barrier height): 1.13 ± 0.13 eV; ii) Pt/HfO₂ barrier height: ~ 2.48 eV; iii) Al/HfO₂ barrier height: ~ 1.28 eV; iv) electron effective mass in HfO₂: 0.1 m_o, where m_o is the free electron mass and v) a trap level at 1.5 ± 0.1 eV below the HfO₂ conduction band which contributes to Frenkel-Poole conduction     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

Group IVB metal oxides high permittivity gate insulators depositedfrom anhydrous metal nitrates

The electrical performance of column IVB metal oxide thin films deposited from their respective anhydrous metal nitrate precursors show significant differences. Titanium dioxide has a high permittivity, but shows a large positive fixed charge and low inversion layer mobility. The amorphous interfacial layer is compositionally graded and contains a high concentration of Si-Ti bonds. In contrast, ZrO₂ and HfO ₂ form well defined oxynitride interfacial layers and a good interface with silicon with much less fixed charge. The electron inversion layer mobility for an HfO₂/SiO_xN_y /Si stack appears comparable to that of a conventional SiO₂ /Si interface     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric

This letter demonstrates reduction in effective work function of tantalum-nitride (TaN) metal gate with erbium-oxide-doped hafnium oxide. We report that TaN effective metal-gate work function can be tuned from Si midgap to the conduction band to meet the work-function requirement of NMOSFETs by incorporating ErO in HfO₂ with an equivalent oxide thickness as low as 1.15 nm. Several other lanthanide-oxide doped hafnium oxides show similar characteristics.     

Border-Trap Characterization in High-κ Strained-Si MOSFETs

In this letter, we focus on the border-trap characterization of TaN/HfO₂/Si and TaN/HfO₂/strained-Si/Si_0.8Ge_0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si_0.8Ge_0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

Thickness Scaling and Reliability Comparison for the Inter-Poly High- κ Dielectrics

In this letter, the inter-poly dielectric (IPD) thickness, scaling, and reliability characteristics of Al₂O₃ and HfO₂ IPDs are studied, which are then compared with conventional oxide/nitride/oxide (ONO) IPD. Regardless of deposition tools, drastic leakage current reduction and reliability improvement have been demonstrated by replacing ONO IPD with high-permittivity (high-kappa) IPDs, which is suitable for mass production applications in the future. Moreover, metal-organic chemical vapor deposition (MOCVD) can be used to further promote dielectric reliability when compared to reactive-sputtering deposition. By using the MOCVD, the charge-to-breakdown (Q_BD) can be significantly improved, in addition to enhanced breakdown voltage and effective breakdown field. Our results clearly demonstrate that high- IPD, particularly deposited by MOCVD, possesses great potential for next-generation stacked-gate Flash memories.     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Structural and electrical properties of HfO2 with topnitrogen incorporated layer

A novel technique to control the nitrogen profile in HfO₂ gate dielectric was developed using a reactive sputtering method. The incorporation of nitrogen in the upper layer of HfO₂ was achieved by sputter depositing a thin Hf_xN_y layer on HfO₂, followed by reoxidation. This technique resulted in an improved output characteristics compared to the control sample. Leakage current density was significantly reduced by two orders of magnitude. The thermal stability in terms of structural and electrical properties was also enhanced, indicating that the nitrogen-doped process is effective in preventing oxygen diffusion through HfO₂. Boron penetration immunity was also improved by nitrogen-incorporation. It is concluded that the nitrogen-incorporation process is a promising technique to obtain high-k dielectric with thin equivalent oxide thickness and good interfacial quality