Border-Trap Characterization in High-κ Strained-Si MOSFETs

In this letter, we focus on the border-trap characterization of TaN/HfO₂/Si and TaN/HfO₂/strained-Si/Si_0.8Ge_0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si_0.8Ge_0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.     

Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO₂, while the subthreshold slope for fixed values of V_g remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an I_on/I_off ratio of more than 2 times 10¹¹ is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Impact of High-κ Offset Spacer in 65-nm Node SOI Devices

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current I_ON and reduce the off leakage current I_OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I_ON/I_OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric     

Operational Voltage Reduction of Flash Memory Using High-κ Composite Tunnel Barriers

We explore the performance of symmetric (low-k/high-k/low-k) and asymmetric (low-k/high-k) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-k materials, were performed under these criteria to minimize the programming voltage V_prog. Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V_prog and choosing the high-k materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V_prog of ~ 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% -40% lower than the prevalent voltages.     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属-氧化物-半导体场效应晶体管的氧化层的影响.对于栅厚为3nm的超薄栅MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响,数值模拟的结果表明:界面粗糙度对电子的直接隧穿有较大的影响,且直接隧穿电流随界面的粗糙度增加而增大,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小.     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

Atomistic Full-Band Design Study of InAs Band-to-Band Tunneling Field-Effect Transistors

Band-to-band tunneling field-effect transistors (BTBT FETs) are expected to exhibit a subthreshold swing (SS) better than the 60-mV/dec limit of conventional metal–oxide–semiconductor FETs at room temperature. Through atomistic modeling of a suite of realistically extended InAs p-i-n single-gate (SG) and dual-gate (DG) ultrathin-body (UTB) and gate-all-around nanowire (GAA NW) devices with a gate length of 20 nm, we demonstrate that such a reduced SS can only be achieved if the electrostatic potential under the gate contact is very well controlled. We find that GAA NWs keep an SS less than 60 mV/dec for diameters larger than 10 nm, while the bodies in DG and SG UTBs must be scaled down to 7 and 4 nm, respectively. Still, all the considered devices are characterized by an on current smaller than the ITRS requirements.      

High-κ Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality—A Mobility Study

The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO₂/HfO₂/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-kappa bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 degC spike for t=1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 degC for t=60 s). For 1000 degC spike-annealed films, where the highest SiO₂/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO₂ and the IL which increases for high-temperature processing     

Comparison of On-The-Fly, DC Id–Vg, and Single-Pulse Methods for Evaluating Threshold Voltage Instability in High-κ nMOSFETs

Stress-induced degradation of the threshold voltage of high-kappa nMOSFETs measured by on-the-fly and single-pulse methods is investigated. It was found that the relaxation of the stress-induced threshold voltage (V_th) shift during stress interruption (sensing) time is primarily governed by the fast detrapping of charges trapped through the fast transient charging (FTC) process. Subtraction of the FTC contribution from the total stress time-dependent V_th shift provides a practical and convenient method for eliminating a major source of V_th relaxation, which results in identical lifetime estimations by the on-the-fly and pulsed methods     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素．数值求解的结果表明：镜像势引起的势垒降低对超薄栅MOS直接隧穿电流有较大的影响．利用WKB近似方法,获得了镜像势对直接隧穿电流影响的定性表达式．镜像势对直接隧穿电流的影响随着栅电压的减小而增大,但是随着栅氧化层厚度的减小而减小．     

镜像势引起的势垒降低对超薄栅MOS结构的直接隧穿电流的影响

随着器件尺寸的不断减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .数值求解的结果表明 :镜像势引起的势垒降低对超薄栅 MOS直接隧穿电流有较大的影响 .利用 WKB近似方法 ,获得了镜像势对直接隧穿电流影响的定性表达式 .镜像势对直接隧穿电流的影响随着栅电压的减小而增大 ,但是随着栅氧化层厚度的减小而减小     

Transport Mechanism of SiGe Dot MOS Tunneling Diodes

The blockage of hole transport due to excess holes In SiGe dots was observed in the MOS tunneling diodes for the first time. The five layers of self-assembled SiGe dots are separated by 74-nm Si spacers and capped with a 130-nm Si. The hole tunneling current from Pt gate electrode to p-type Si dominates the inversion current at positive gate bias and is seven orders of magnitude higher than the Al gate/oxide/p-Si device. The large work function of Pt is responsible for the hole transport current from Pt to p-Si. The incorporation of SiGe dots confines the excess holes in the valence band and forms a repulsive barrier to reduce the hole transport current from Pt to SiGe dots by 2-3 orders of magnitude in comparison with the Pt/oxide/p-Si device. This repulsive barrier also reduces the hole tunneling current from SiGe dots to Pt at negative gate bias.     

A Program-Erasable High-κ Hf0.3N0.2O0.5 MIS Capacitor With Good Retention

We describe a programmable-erasable MIS capacitor with a single high-k Hf_0.3N_0.2O_0.5 dielectric layer. This device showed a capacitance density of ~6.6 fF/mum², low program and erase voltages of +5 and -5 V, respectively, and a large DeltaV_fb memory window of 1.5 V. In addition, the 25degC data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf_0.3N_0.2O_0.5.     

功率MOS器件的结构与性能

电力电子器件的结构决定其性能,而器件的性能又决定电路的性能。根据此原理,本文分析比较了近十年来十种实用的具有新型的功率MOS器件的结构与性能特点,包括：NPT－IGBT、PT－IGBT、SDB－IGBT、Trench MOSFET、Trench IGBT、Cool MOSFET、BiMOSFET、HV－IGBT、HS－IGBT、RB－IGBT。     

Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- κ/Metal-Gate Device Structures

This letter reports, for the first time, the observation of mechanical stress from metal-gate layer on the Si nanowires formed by the top-down scheme. High-kappa (HfO2 ~ 5 nm) and metal-gate (TaN ~ 100 nm) are evaluated on Si nanowires having ~5-7 nm diameter. While no significant mechanical effect is observed after high-kappa deposition, the TaN metal layer is found to viciously stretch and twist the straight wires. The wire lengths increase significantly (~3%), which suggests that the Si nanowires are subjected to large tensile strain ( > 4 GPa), assuming that the wires obey Hooke's law with Young's modulus ~150 GPa for bulk Si. Interestingly, the twisted nanowires maintained their physical continuity, as demonstrated by the excellent performance of the fully functional gate-all-around MOSFETs fabricated with the wires as channels.     

应用于EEPROM的超薄SiO2 TDDB特性的研究

阐述了应用于ＥＥＰＲＯＭ中的超薄隧道氧化层随时间的击穿特性,比较和分析了不同的可靠性测试方法,并对超薄氧化层生长工艺的优化进行了探讨。     

Oxide current in MOS transistors operated under charge pumping conditions

The present paper describes an alternative approach for isolating the oxide current from the gate current (GC) and its use for characterizing the bulk oxide in MOS transistors. The method is based on measurements of the gate as well as the substrate currents of MOS transistors pulsed by a train of square wave pulses under charge pumping conditions.The measurements are done on various experimental devices and different gate and drain/source voltage biasing. The GC has been measured and was found to be of typical behavior when it is plotted with respect to the gate voltage. Moreover, the gate and substrate currents are found to be of complementary shapes when plotted with respect to gate voltage. This behavior is made useful in studying and characterizing the oxide and the interface of MOS transistors.