Reducing clock jitter by using Muller-C elements

A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element?s output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogueto- digital conversion, and in clock distribution networks for VLSI systems.     

基于ADC的时钟jitter测试平台的研究

本文实现了一种利用高速模数转换器(ADC)采样测量时钟jitter的硬件测试平台.文中针对高速、高分辨ADC的特性,导出时钟Jitter对输出码密度的影响,根据这层关系可以反推出时钟Jitter的大小.同时介绍了如何在硬件上产生高速、可以控制的时钟jitter.最后通过ModelSim和Matlab对这个平台进行仿真分析,结果表明这种方法不需要高性能仪器,且具有高分辨和低时耗等特点.     

Self-correcting clock recovery circuit with improved jitter performance

In the letter we present a new clock recovery circuit with self-correction of the position of the retiming clock, which shows the reduction of the output jitter by deleting the phase difference of ? radians in the output of the phase detector existing in Hogge's scheme.     

基于时钟抖动跟踪的PLL工作稳定性监测

针对复杂设备中PLL工作稳定性监测问题,建立了一种基于时钟抖动跟踪技术的PLL监测模型.采用迟延系统保证输入时钟与PLL时钟同相,消除了输入时钟抖动对PLL抖动判断的影响,利用先验知识序列消除了判断序列中确定分量,确保模型判断序列中只有PLL输出时钟抖动引起的噪声分量,利用计数器对噪声分量进行采集周期内统计,可以判定P...     

Fast acquisition clock and data recovery circuit with low jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.     

一种适用于相变存储器的低抖动锁相环时钟

A fully integrated low-jitter,precise frequency CMOS phase-locked loop(PLL) clock for the phase change memory(PCM) drive circuit is presented.The design consists of a dynamic dual-reset phase frequency detector(PFD) with high frequency acquisition,a novel low jitter charge pump,a CMOS ring oscillator based voltage-controlled oscillator(VCO),a 2nd order passive loop filter,and a digital frequency divider.The design is fabricated in 0.35μm CMOS technology and consumes 20 mW from a supply voltage of 5 V.In terms of the PCM’s program operation requirement,the output frequency range is from 1 to 140 MHz.For the 140 MHz output frequency,the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.     

用于星光III激光同步系统的低抖动时钟整形技术

针对参考时钟源高电平脉冲宽度窄(小于2 ns)和本底噪声大的问题,通过使用一种时钟低抖动整形技术方案,使参考时钟经过锁相整形后高电平脉冲宽度大于3 ns、锁相相位时间抖动均方根(RMS)值小于5 ps。目前该方案已成功用于星光III激光装置的联机实验,情况良好,对其他类似需要精密时钟的装置具有极大的借鉴意义。     

正弦平滑时间幅度调制的低抖动时钟信号产生

针对低抖动时间幅度调制时钟信号引入滤波失真的问题,提出了一种正弦平滑改进的时间幅度调制方法,对时间幅度调制时钟信号进行正弦函数平滑处理,在保持过零点抖动较小前提下,改善时钟信号的频谱特性。仿真分析和现场可编程门阵列(Field Programmable Gate Array, FPGA)硬件实现结果表明,产生的正弦平滑时间幅度调制时钟信号有效抑制了带限失真,优于普通的数字压控振荡器和原始的时间幅度调制时钟信号。     

The jitter time-stamp approach for clock recovery of real-timevariable bit-rate traffic

When multimedia streams arrive at the receiver, their temporal relationships may be distorted due to jitter. Assuming the media stream is packetized, the jitter is then the packet's arrival time deviation from its expected arrival time. There are various ways to reduce jitter, which include synchronization at the application layer, or synchronization at the asynchronous transfer mode (ATM) adaptation layer (AAL). The new source rate recovery scheme called jitter time-stamp (JTS) provides synchronization at the ATM adaptation layer 2 (AAL2) which is used to carry variable bit-rate traffic such as compressed voice and video. JTS is implemented, and experiments have shown that it is able to recover the source rate     

时钟提取与抖动衰减数字锁相环设计研究

文章简要介绍了数字锁相环(DPLL)的工作原理,重点提出了用于V5接口芯片中的时钟提取锁相环和抖动衰减锁相环的设计,并对其进行了分析．     

时钟抖动和相位噪声对采样系统的影响

随着直接中频采样的更高分辨力数据转换器的上市，系统设计师必须对低抖动时钟电路做出有助于性能与成本折衷的抉择。制造商用来规定时钟抖动的很多传统方法并不适用于数据转换器，或者说，充其量也只能反映问题的一部分。如果对时钟电路的规范和设计没有恰当的了解，你就不能实现这些数据转换器的最佳性能。     

Timing jitter in soliton transmission with up- anddown-sliding-frequency guiding filters

We derive an analytical expression for the variance of the timing jitter of a soliton transmission system using sliding-frequency guiding filters, taking into account the third-order filter term. An improved analytical result for the upper limit of the sliding rate for stable soliton propagation is also obtained. We show that the variance of timing jitter is significantly increased by the sliding action. As a consequence of the third-order filter contribution, the timing jitter is lower in a system with down-sliding compared with the up-sliding regime at the same sliding rate     

基于线性调频信号的数模转换器时钟抖动误差分析

数模转换器的时钟抖动引起输出信号的误差,该误差会影响后继的信号处理.本文分析了数模转换器中输入为线性调频信号时,由时钟抖动引起的误差.首先给出了该误差平均功率表达式,然后根据该表达式推导出输出信噪比的近似计算公式,最后对影响信噪比的各种因素进行讨论,其中信号的带宽及时钟抖动参数的增大均会降低输出信噪比,而调频斜率的变化对输出信噪比影响较小,采样频率的增大可以在一定程度上提高信噪比.仿真结果验证了信噪比计算公式的正确性,并给出了信噪比随各种因素变化的趋势.     

Collision-induced timing jitter reduction by periodic dispersionmanagement in soliton WDM transmission

The authors propose to use dispersion management to reduce collision-induced timing jitter in soliton WDM transmission. The performance of dispersion-managed fibres is compared numerically to dispersion-decreasing and uniform dispersion fibres with up to eight channels, and it is shown that dispersion management can provide the best performance     

A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

The performance of continuous time delta-sigma modulators is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback DACs. To mitigate that effect, a dual switched-capacitor-resistor feedback DAC technique is proposed. The architecture has the additional benefit of reducing the typically high switched-capacitor-resistor DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. The feedback technique has been implemented with a third order, 3-bit delta-sigma modulator for a low power radio receiver, in a 65 nm CMOS process, where it occupies an area of 0.17 mm². It achieves an SNDR of 70 dB over a 125 kHz bandwidth with an oversampling ratio of 16. The power consumption is 380 μW from a 900 mV supply.     

Reduction of Gordon-Haus jitter in soliton transmission systems byoptical phase conjugation

The effect of optical phase conjugation on Gordon-Haus jitter in long-distance soliton communication systems is considered. In-line optical phase conjugation at an optimal point two-thirds of the way down the system reduces the rms jitter by a factor of three. A post-transmission-line compensation scheme based on optical phase conjugation and soliton-supported dispersion compensation reduces the rms jitter by a factor of two     

Data sequence coding for low jitter timing recovery

The letter considers the timing content of a random data sequence and presents a line coding technique to achieve reliable, low-jitter timing recovery.     

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer andtemperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0°C to 85°C. The circuits were fabricated on a generic 0.5-μm digital CMOS process     

采样时钟抖动在弱光信号检测中的影响分析

信号采样是弱光信号检测的关键技术环节,由于采样时钟抖动引起的采样信号的输出误差会影响后续的信号检测和处理。为此,分析了输入光信号为近高斯分布波形时由时钟抖动引起的采样误差,推导出了采样输出的信噪比损失公式,讨论了采样带宽、输入信噪比以及信号脉宽对输出信噪比损失的影响,最后以取样积分检测技术为对象,计算了在不同累积次数的条件下采样抖动对取样积分检测性能的影响,对弱光信号检测中的采样时钟选取具有一定的指导意义。     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.