数字卫星广播系统采样时钟同步方法

针对数字卫星广播系统中采样时钟偏差会严重影响接收性能的问题,提出了一种采样频率和相位同步方法。该方法利用迟早门进行采样误差估计,利用Farrow滤波器进行插值处理。通过采样频偏调整环路控制Farrow滤波器,实现采样频率和相位同步。实验结果表明,该方法能够在高强度噪声干扰和较大载波频偏环境下,快速准确的实现采样时钟同步。该方法还可以广泛应用于数字地面广播、数字移动广播等多个领域。     

Error-driven edge selection for ΣΔ modulated signals tosuppress in-band noise due to non-uniform sampling

A method for suppressing the in-band noise of ΣΔ-modulated signals due to non-uniform sampling is proposed. This method enables the use of the over-sampling clock generated from a fractional programmable generator without significant degradation in the signal-to-(noise+distortion) ratio (SNDR). The sampling frequency is controlled with a frequency resolution of 5.4 Hz without an analogue PLL. Experimental results for the voice band application of the ΣΔ-modulated 1 bit DAC show that the SNDR can be maintained at >70 dB, for sampling rates in the range 7.1-7.8 kHz     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

The Effects of Polarization-Mode Dispersion on the Phase of the Recovered Clock

The impact of polarization-mode dispersion (PMD) on the phase of the recovered clock in the receiver is analyzed. The effects of first-order PMD on different clock-recovery configurations utilized for return-to-zero (RZ) and non-RZ (NRZ) formats are studied. Closed-form expressions relating the PMD-induced sampling time shift with the differential group delay and the power ratio between the principal states of polarization are obtained for each high-Q filter-based clock recovery. An experimental validation at 10 Gb/s is also shown for the case of NRZ data format     

A sampling technique and its CMOS implementation with 1 Gb/sbandwidth and 25 ps resolution

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 μm CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution     

Clock jitter impact on the performance of general charge sampling amplifiers

In this paper we present the detailed performance analysis of general charge sampling amplifiers (CSAs) due to clock jitter impact. A simple analytical model for quick estimation of the signal-to-noise ratio by considering clock jitter alone as a noise source is proposed for a general CSA. The proposed analytical model is compared with a previously published more complex model and also with the well known voltage sampling. Simulation results showing the performance due to clock jitter impact of CSAs are also presented here to confirm the proposed analytical model. The potential advantages of clock jitter tolerances in charge sampling are discussed in detail.     

Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling

This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular, the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved converters in the presence of substrate noise.     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

Sample Clock Offset Detection and Correction in the LTE Downlink

The narrow subcarrier spacing and wide bandwidth arrangement in the LTE downlink produce a vulnerability to sample clock mismatch between the transmitting and receiving data converters. Without high precision sampling clock frequencies, a high level of inter-carrier interference (ICI) is introduced, yielding undesirable performance. In this article, a method to jointly estimate and correct sampling frequency mismatch is proposed. The proposed method uses information already known to the receiver, operates strictly in the time domain and does not require the aid of pilot symbols or other frequency domain information. The method allows clocks with lower precision to be used with minimal performance degradation. Results are presented using MATLAB simulation as well as an FPGA hardware implementation.     

Digital Encoding of Phase Shift Keying Voiceband Data Signals

Computer simulation was used to evaluate the performance of eleven coder/decoders (CODEC's) with phase shift keying (PSK) and differential PSK(DPSK) voiceband data signals. The CODEC's were PCM, differential PCM and delta modulation systems designed for speech and operating at bit rates from 16 to 64 kbits/s. The voiceband data signals processed by these CODEC's were demodulated to determine the phase error caused by the CODEC. The phase error introduced by the CODEC's is a function of the phase of the CODEC sampling clock relative to the data modem bit clock. Some of the statistics of the phase error are presented. Three performance metrics were used to evaluate the performance of these CODEC's-signal to quantizing noise ratio, variance of the phase error and maximum value of the phase error.     

一种低功耗高性能自举采样开关

提出了一种基于TSMC 40 nm/0.9 V CMOS工艺设计的适用于音频范围的低功耗高性能栅压自举采样开关电路。通过PMOS晶体管的衬底和漏极相连接代替了时钟放大模块,极大降低了电路整体的功耗。在输入端增加了一个NMOS晶体管,随着开关时钟的开启/关闭,通过抑制核心采样晶体管的体效应,可以有效提高开关线性度。鉴于音频信号的范围,选用频率为19.53 kHz、幅值为0.3 V的正弦波信号进行10 MHz采样频率的高速采样仿真,与传统结构相比,有效位数(ENOB)、信噪比(SNR)、无杂散动态范围(SFDR)和总谐波失真(THD)四项性能指标分别提升了5.5%、3.7%、13.8%和5.4%,并且功耗降低了36.8%。     

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.     

用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为 0.31/-0.46LSB,差分非线性为 0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.     

A programmable clock generator that uses noise shaping and itsapplication in switched-capacitor filters

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-μm CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCF's are reported     

基于FPGA的任意相位时钟管理器的设计

在通信双方为同源时钟的前提下,为保证时钟在接口处把所有数据都正确采样进来,利用Altera的综合开发平台Quartus II,实现了采样时钟相位根据输入数据相位自动调整,使采样时钟能找到最佳的采样时间来采样外来数据。任意相位时钟管理器可以产生高精度动态相位的时钟信号。     

基于随路时钟恢复的多源数据光纤传输系统

针对数据互联网络中多源高速并行数据实时传输的问题,提出了一种基于随路时钟恢复的多源数据光纤传输系统,详细介绍了其工作原理和设计思想.系统将现场可编程逻辑门阵列(FPGA)内部高速收发器与专用数字锁相环相结合,给出了随路时钟恢复与数据流量控制的具体实现过程.相比于现有的各类高速并行数据传输解决方案,该系统具备可软件定义的数据接入能力,也能支持更加灵活的随路时钟动态范围.同时,通过设计精简合理的帧结构,推导数据位宽与随路时钟之间的约束关系,有效提高了系统传输带宽.测试结果表明,该系统工作稳定可靠,实时传输效果好,时钟恢复精度可达100 fs,扩展了串并转换与并串转换技术的应用领域.     

10 GB/s bit-synchronizer circuit with automatic timing alignment byclock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effective sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping circuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5-μm CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm² dissipating 550 μW while the digital-to-analog converter occupies 0.28 mm² dissipating 600 μW     

基于FPGA的S/PDIF接收机数据解码系统的实现

为了准确接收并提取专业音频设备所发出的S/PDIF数据信号,方便后续数字音频处理模块的信号处理工作,减少因使用专业集成电路带来的额外成本,设计了基于FPGA的通用S/PDIF接收解码电路。该电路首先利用数字鉴相方式从S/PDIF信号中恢复出采样时钟,然后根据恢复出的采样时钟对信号进行采样,获得串行数据。随后电路对其进行帧同步处理以区分不同的数据段,最终按照S/PDIF的编解码规则对其进行解码后,以并行方式输出给后续音频处理模块进行进一步处理。