Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers

We describe a general offset-canceling architecture for analog multiplication using chopper stabilization. Chopping is used to modulate the offset away from the output signal where it can be easily filtered out, providing continuous offset reduction which is insensitive to drift. Both square wave chopping and chopping with orthogonal spreading codes are tested and shown to reduce the offset down to the microvolt level. In addition, we apply the nested chopping technique to an analog multiplier which employs two levels of chopping to reduce the offset even further. We discuss the limits on the performance of the various chopping methods in detail, and present a detailed analysis of the residual offset due to charge injection spikes. An illustrative CMOS prototype in a 0.18 mum process is presented which achieves a worst-case offset of 1.5 muV. This is the lowest measured offset reported in the DC analog multiplier literature by a margin of two orders of magnitude. The prototype multiplier is also tested with AC inputs as a squarer, variable gain amplifier, and direct-conversion mixer, demonstrating that chopper stabilization is effective for both DC and AC multiplication. The AC measurements show that chopping removes not only offset, but also 1/f noise and second-order harmonic distortion.     

A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifier's architecture. The offset voltage of a single-stage folded cascode amplifier has been programmed to a minimum of plusmn25 muV in a 0.5 mum digital CMOS process. The long-term offset voltage drift has been calculated to be less than 0.5 muV over a period of 10 years at 55degC from a thermionic emission model for floating-gate charge loss. The offset voltage varies by a maximum of 130 muV over a temperature range of 170degC, thereby making this a viable approach to offset cancellation     

一种适用于微传感器读出电路的低噪声、低失调斩波放大器

提出一种适合微传感器读出电路的高精度折叠共源共栅放大器.基于斩波技术和动态元件匹配技术,降低了折叠共源共栅放大器的噪声和失调,采用低阻节点斩波的方法和低压共源共栅电流镜扩大了放大器可处理的输入信号带宽和输出电压摆幅.芯片在0.35μm 2P4M CMOS工艺下设计并流片,测试表明在3.3V的典型电源电压和100kHz的斩波频率下,斩波放大器具有小于93.7μV的输入等效失调电压典型值,19.6nV/Hz的输入等效噪声,开环增益达83.9dB,单位增益带宽为10MHz.     

CMOS Multistage Preamplifier Design for High-Speed and High-Resolution Comparators

This brief describes a design technique for multistage preamplifiers of the type commonly used in high-performance comparators. Following the examination of multistage preamplifier responses in both the spectral and time domains, and a consideration 1/f noise attenuation in topologies employing offset storage capacitors, a procedure for optimizing both the number of stages and the offset storage capacitance is presented. As a demonstration vehicle, a comparator with a 13-Msample/s conversion rate and 200-muV minimum input resolution is designed for realization in a 0.4-mum CMOS technology under the constraint of a power dissipation of 250 muW when operating from a 2.5-V supply. In this design, the effective input signal is 33 muV for the minimum input resolution of 200 muV due to signal corruption from circuit noise and residual error from incomplete settling     

一种适用于传感器信号检测的斩波运算放大器

提出一种适合传感器微弱信号检测应用的全差分低噪声、低失调斩波运算放大器。采用两级折叠共源共栅运放结构,基于斩波稳定及动态元件匹配技术,通过在运放低阻节点的电流通路上添加斩波开关的设计方式,增加了运放的输入信号带宽和输出电压摆幅。芯片采用TSMC 0.18μm 1P6MCMOS工艺实现。测试结果表明,在1.8V电源电压,25kHz输入信号和300kHz斩波频率下,斩波运放输入等效失调电压小于120μV,在10Hz～1kHz之间,输入等效噪声为5nV/Hz^1/2,最高开环增益为84dB,单位增益带宽为4MHz。     

A Sub-1-V Low-Noise Bandgap Voltage Reference

A new sub-1-V bandgap voltage reference is presented in this paper, which has advantages over the prior arts in terms of output noise and compatibility with several fabrication processes. The topology allows the reference to operate with a supply voltage as low as 1 V by employing the reverse bandgap voltage principle (RBVP). It also has an attractive low-noise output without the use of a large external filtering capacitor. The design was fabricated with a 0.5-mum BiCMOS process, but it is compatible with most CMOS and BiCMOS fabrication processes. The entire die area is approximately 0.4 mm², including all test pads and dummy devices. Theoretical analysis and experimental results show that the output noise spectral density is 40 nV/radicHz with a bias current of 20 muA. Moreover, the peak-to-peak output noise in the 0.1-10 Hz band is only 4 muV. The untrimmed reference has a mean output voltage of 190.9 mV at room temperature, and it has a temperature coefficient in the -40degC to +125degC range of 11 ppm/degC (mean) with a standard deviation of 5 ppm/degC.     

A Programmable 210-μV Offset Rail-to-Rail Gm –C Filter

Low input-referred offset performance and linearity in analog filters are critical design parameters, yet transistor mismatch limitations are a severe hindrance. Programmability is also a feature of growing significance because high performance state-of-the-art systems must adapt on-the-fly to various operating conditions, as is the case in battery-operated electronics where systems traverse through idle, alert, and high performance modes in an effort to conserve energy and extend battery life. This paper presents a continuous and programmable first-order G_m-C filter with sub-millivolt offset performance. Low offset is achieved by auto-zeroing and continuity by ping-ponging between two transconductors, all under the construct of a compact and bandwidth-efficient circuit topology. The proposed G_m-C circuit was fabricated with AMI's 0.5-mum CMOS process technology and achieved an input-referred offset of less than 210 muV, hand-over glitches of less than 40 mV, and 57 dB of linearity over the rail-to-rail input span for a lithium-ion battery supply range of 3 to 4.2 V. The bandwidth and gain of the filter were programmable from 1.1 to 6.5 kHz and 1.27 to 29.1 V/V, respectively, both with better than 3.2% resolution.     

一种用于水听器电压检测的模拟前端电路

提出了一种用于水听器电压检测的模拟前端电路,包括低噪声低失调斩波运算放大器,跨导电容(gm-C)低通滤波器,增益放大器三部分主体电路;低噪声低失调斩波运算放大器用于提取水听器前端传感器输出的微弱电压信号;gm-C低通滤波器用于滤除电压信号频率外的高频噪声和高次谐波;最后经过增益放大器放大至后级模数转换器的输入电压范围,输出数字码流;芯片采用台积电(TSMC)0.18μm单层多晶硅六层金属(1P6M)CMOS工艺实现。测试结果表明,在电源电压1.8 V,输入信号25 kHz和200 kHz时钟频率下,斩波运放输入等效失调电压小于110μV;整体电路输出信号动态范围达到80 dB,功耗5.1 mW,满足水听器的检测要求。     

A 1-V CMOS Current Reference With Temperature and Process Compensation

A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, V_REF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, I_REF , nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-mum CMOS process. Results from nineteen samples measured over a temperature range of 0degC to 100degC , showed values of I_REF of 144.3 muA plusmn 7% and V_REF of 610.9 mV plusmn 2% due to the combined effect of temperature and process variations.     

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW     

A 60 μW 60 nV/√Hz Readout Front-End for Portable Biopotential Acquisition Systems

There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A Tunable Pseudo-Differential OTA With $-78~{hbox {dB}}$ THD Consuming 1.25 mW

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-mum CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-V_pp input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption.     

A Current-Feedback Instrumentation Amplifier With 5 $mu{hbox{V}}$ Offset for Bidirectional High-Side Current-Sensing

This paper describes an instrumentation amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 $mu{hbox{V}}$ , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The instrumentation amplifier was realized in a 0.8 $mu{hbox{m}}$ BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 ${hbox{mm}}^{2}$ .      

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology

A 71-80 GHz amplifier using 0.13-mum standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This four-stage cascade thin-film microstrip amplifier achieves the peak gain of 7.0 dB at 75 GHz. The 3-dB frequency bandwidth range is from 71 to 80 GHz. The amplifier demonstrates the highest amplification frequency and smallest chip size among previous published millimeter-wave (MMW) 0.13-mum CMOS amplifiers.     

An Implantable CMOS Front-End System for Nerve-Signal Sensors

An analog front-end dedicated to processing of cuff-recorded human nerve signals is presented in this paper. The system is comprised of a low-noise preamplifier and an A/D converter (ADC) for quantizing the recorded nerve signal. The instrumentation amplifier utilizes CMOS transistors biased in the weak/moderate inversion region at a relatively high current for low thermal noise performance and achieves low flicker noise performance through chopper stabilization. The resulting measured equivalent input referred thermal noise is 6.6 nV/√Hz at a chopping frequency of 20 kHz. A two-stage design is implemented which achieves a measured amplification of 72.5 dB over a signal bandwidth of 4 kHz. For the ADC, a third order ΣΔ-modulator employing a continuous-time (CT) loopfilter was implemented. Each of the integrators in the loop-filter are implemented as G _m ?C elements. For a sampling frequency of 1.4 MHz, the measured SNDR for the ADC is 62 dB, whereas the dynamic range (DR) is 67 dB over a 4 kHz bandwidth, equivalent to a resolution of 10 bits. The system draws a current of 196 μA from a 1.8 V supply thus consuming approximately 350 μW excluding buffers and bias circuitry.     

A robust CMOS compander

A robust CMOS compander circuit meeting all of the requirements for analog cellular telephony and using an improved sigma-delta compander topology is presented. Rather than digitizing and reconstructing the input signal using a sigma-delta modulator as has been done previously, only the amplitude path is digitized while the voice path remains analog. The amplitude information is obtained digitally, and is reduced to a single bit using a first-order sigma-delta modulator. Performing this function digitally eliminates problems due to analog offsets and in implementing the long time constant required. The output signal is formed by gating the analog input signal under control of the amplitude signal. The expander and compressor circuits each consist of a single op amp and 2000 gates of digital logic, and have been implemented on 0.8-μm CMOS processes. The ADC for the amplitude path uses a compact switched-capacitor second-order sigma-delta modulator implemented using a single amplifier. No external components are required. Tracking error for the compressor was measured to be less than 0.3 dB over a 60-dB input range when operating on a 3.0-V supply. The test time, when compared to conventional compander implementations, is considerably reduced