Electrothermal simulations in punchthrough and nonpunchthroughIGBT's

The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs     

SC电路混合分析的一种方法

本文提出了ＳＣ电路混合分析的一种方法，此法特别适合于计算机辅助电路分析，并且所推导的ＳＣ电路混合议程与状态议程有着紧密的联系，由此可方便地求得ＳＣ电路的频域传递函数。     

EL characteristics of a TFEL/TFT stacked structure display devicedriven by a HV-Si·TFT circuit

TFEL/TFT stacked structure display devices were fabricated onto a quartz substrate. By using a HV-TFT circuit as the basis of a TFEL/TFT device, an EL device on the TFT circuit can be switched at a sufficiently low signal line voltage of V_s=2-3 V. The maximum brightness of the TFEL/TFT device is 230 cd/m² and the ON/OFF brightness ratio is more than 90 between Vs=0 and Vs=4 V at a V_app frequency of 5 kHz and a voltage of 50. Evaluation of the dynamic behavior of TFT circuits using multichannel HV-Si·TFT's showed that the rise time of the fundamental TFT circuit at the EL driving point of the circuit was about 20 μs and that the hold time of the circuit was about 70 mS. The rise time and the fall time of the luminescence were each about 20 μs. The memory characteristics of the TFEL/TFT device showed that the hold time of the luminescence was about 40 mS. These dynamic characteristics of the TFEL/TFT stacked structure device satisfy the conditions required for a flat panel display     

用于GaN HEMT栅驱动芯片的快速响应LDO电路

设计了一种用于GaN高电子迁移率晶体管(High-Electron-Mobility Transistor,HEMT)器件栅驱动芯片的快速响应低压差线性稳压器(Low Dropout Regulator,LDO)电路,可为高速变化的数字电路提供快速响应的供电电压。该电路采用动态偏置结构,通过在大负载发生时给误差放大器增加一个额外的动态偏置结构,来加快输出端的瞬态响应速度。基于0.18μm BCD工艺,完成了电路设计验证。仿真结果显示LDO瞬态响应时间小于0.5μs,可满足频率达1 MHz的GaN HEMT器件栅驱动芯片应用要求。     

Programmable time-multiplexed switched-capacitor variable equalizerfor arbitrary frequency response realizations

A time-multiplexed digitally-programmable switched-capacitor (SC) variable equalizer which allows the realization of arbitrary frequency responses is presented. The circuit performs the same operation as a cascade of N second-order programmable equalizers, where N is also the multiplexing order. Except the storing capacitors, the rest of the circuitry is shared for all individual equalizer functions (channels), resulting in silicon area savings higher than 60% with respect to a direct circuit implementation for N=4. The impact on circuit performance of crosstalk effects is discussed. Experimental results of a 3-V timesharing SC equalizer architecture fabricated in a CMOS 1.2 μm technology are given for different values of the multiplexing order. The circuit has been designed to be incorporated in a programmable hearing aid device     

Low-cost back contact silicon solar cells

Back-contacted solar cells offer multiple advantages in regard of reducing module assembling costs and avoiding grid shadowing losses. The investigated emitter-wrap-through (EWT) device design has an electrical connection of the front emitter and the rear emitter grid in form of small holes drilled into the crystalline silicon wafer. The obtained cell structure is especially suitable for low-cost base material with small minority carrier diffusion lengths. Different industrially applicable solar cell manufacturing processes for EWT devices are described and compared. The latest experimental results are presented and interpreted; the photocurrent is found to be distinctly increased. The relation between open circuit voltage and rear side passivation is discussed based on two-dimensional (2-D) computer simulations     

一种超高速ECL多模分频器

本文着重介绍一种超高速ECL多模分频器的电路原理、电路设计、版图设计、工艺设计及研制结果。通过计算机模拟及优化设计,研制的分频器电路具有分频模数大、分频模数多、工作频率高、输出驱动能力强、输入动态范围宽、输入与输出能与CMOS/TTL兼容和工作温度宽以及使用方便等特点。     

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.     

一种用于高压电平位移电路结构的准三维模拟方法

A new quasi-three-dimensional （quasi-3D） numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

触发器电路的分析

触发器的电压波形图是学习计算机接口及控制课程中时序图的基础,通过对不同电路结构的触发器进行分析,掌握其动作特点;并特别对不同电路结构触发器的不定态的理解进行了详细的分析,总结出主从触发器电路电压波形图的描绘方法。     

Monolithic integration of laser diodes, photomonitors, and laser driving and monitoring circuits on a semi-insulating GaAs

A monolithic optoelectronic-integrated circuit (OEIC) incorporating laser diodes, photomonitors, and laser driving and monitoring circuits has been fabricated on a semi-insulating GaAs substrate. The structure and circuit design considerations, the fabrication processes, and the static and dynamic characteristics of the device are described. The device has been successfully operated up to 2 Gbit/s.     

Inductorless DC-to-DC converter with high power density

A new type of switching-mode power supply containing no inductors or transformers is proposed. The controlled transfer of energy from a unregulated DC source to a regulated output voltage is realized through a switched-capacitor (SC) circuit. A duty-cycle control is used; the driving signals of the transistors in the SC circuit are determined by the feedback circuit. The absence of magnetic devices makes possible the realization of power converters of small size, low weight and high power density, able to be manufactured in IC technology. High efficiency, small output voltage ripple and good regulation for large changes in the input voltage and/or load values are other positive features of the new type of DC-to-DC power converter. The input-to-output voltage conversion ratio is flexible; the same converter structure can provide a large range of constant desired values of the output voltage for a given input voltage, by predetermining the steady-state conversion ratio. The frequency response shows good stability of the designed converter. The experimental results obtained by using a prototype of a step-down SC-based DC-to-DC converter confirmed the theoretical expectations and the computer simulation results.<>     

随钻声波测井仪电路系统设计与实现

该文针对随钻声波测井技术的特点以及井下仪器的工作要求,着重阐述了随钻声波测井仪井下电路系统、配套维护装置以及上位机软件的设计与实现.上位机是随钻声波测井仪的可视化控制中心,负责向井下电路发送命令、数据以及升级文件;维护装置的主要功能是完成上位机与井下电路之间的命令交互、功能检测和数据传输,是井下电路和上位机通信的纽带;井下电路主要完成对声波小信号的接收、调理、采集等任务,并将采集的数据结果上传.另外,井下电路系统还具有内嵌自测试功能,能够通过对自检信号采样达到校准采样精度的目的.实验结果表明,该电路系统噪声小,有较强的噪声抑制能力等,通道间波形一致性较好,能在井下恶劣环境中稳定可靠地工作,能够满足实际测井作业的需要.     

Use of focused-ion-beam and modeling to optimize submicron MOSFETcharacteristics

An asymmetrical MOSFET structure is formed by using a focused-ion-beam implantor to create a p⁺ channel doping next to the source. This work builds on previous efforts by providing a uniquely tailored doping profile through the use of localized beams. An investigation shows that the output resistance improves, detrimental hot-electron effects diminish, and threshold voltage stabilizes as channel length is reduced. The improved output resistance is especially beneficial to analog applications where enhanced current source characteristics often lead to significantly better circuit operation. Improvements in device performance are attributed to the reduction of the pinchoff region, which is clarified with the help of detailed hydrodynamic device simulations. A two-transistor equivalent circuit model has been developed which reflects the device structure     

利用可编程器件设计移位寄存器

随着科学技术的发展 ,特别是微电子技术和计算机技术的发展 ,数字逻辑电路的实验手段也不断得到更新、完善和发展。从 80年代中期开始 ,可编程逻辑器件 (PLD)的出现让人们告别了在印刷电路板上拼凑大规模电路的时代。由于可编程逻辑器件与分立逻辑器件相比较具有速度快、容量大、功耗低、可靠性高等众多优点 ,因此被广泛用来取代分立元件逻辑实验。本文介绍一种利用可编程器件设计四位环形移位寄存器的方法。     

开关电容滤波器的计算机辅助分析

开关电容滤波器(SCF)在集成电路中占有极为重要的地位,它具有集成度高,设计精度高,温度稳定性好,并可采用成熟的MOS工艺实现等优点,为了提高电路设计的效率和准确性,计算机辅助分析受到越来越多的重视。 本文采用SPICE电路模拟程序和等效电路变换方法,讨论了对SCF电路进行计算机辅助分析的步骤和方法,并用此方法设计了一个用于脉码调制(PCM)电话系统的D3通道的五阶椭圆低通滤波器,所得结果与传输函数结果一致。     

A Large-Signal Model for the GaAs MESFET

An analytic Iarge-signal model for the GaAs FET is described which relates the terminal currents to the instantaneous terminal voltages and their time derivatives. It incorporates the device geometry and semiconductor parameters as well as the device parasitic circuit elements. The model is fast and efficient when implemented on a computer and is in a form suitable for large-signal circuit design and optimization.     

Trade-off analysis of the p-base doping on ruggedness of SiC MOSFETs

Reliability represents a very important factor for the design of Silicon Carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs). Ruggedness of the device during abnormal operating conditions like the short circuit (SC) and avalanche conduction (during unclamped inductive switching - UIS) is an important aspect of reliability. Often, variation in design parameters to improve ruggedness during SC and UIS shows negative impact on the nominal operating performance. This paper presents a comprehensive analysis of the impact of modification of p-base doping on the performance of a 1.2 kV SiC MOSFET during SC and UIS by means of TCAD simulations. The improvement in MOSFET ruggedness by optimizing the p-base doping and its influence on the nominal operating performance is evaluated.