Micro breakdown in small-area ultrathin gate oxides

The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.     

Radiation-induced depassivation of latent plasma damage

Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/SiO₂ interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices.     

Localized oxide degradation in ultrathin gate dielectric and its statistical analysis

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots.     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

F等离子体处理 AlGaN/GaN HEMT击穿电压和电流崩塌研究

F等离子体处理工艺被广泛的应用于 AlGaN/GaN HEMT增强型器件的研制和栅前处理工艺。本文研究了低功率F处理 AlGaN/GaN HEMT的击穿特性和电流崩塌特性。随着F处理时间的增加,饱和电流下降,阈值电压正向移动。对不同F处理时间的器件肖特基特性分析后发现,120s的F处理后器件栅泄漏电流明显减小,器件击穿电压提高,当F处理时间大于120s后,由于长时间F处理带来的损伤器件栅泄漏电流没有继续减小。采用不同偏置下的双脉冲测试对不同F处理时间的电流崩塌特性进行了研究,低功率F处理后没有发现明显的电流崩塌现象。     

反应离子刻蚀铝中nMOS 器件的等离子充电损伤

介绍在等离子工艺中的等离子充电损伤,并且利用相应的反应离子刻蚀(RIE)Al的工艺试验来研究在nMOSFET器件中的性能退化。通过分析天线比(AR)从100:1到10000:1的nMOSFET器件的栅隧穿漏电流,阈值Vt漂移,亚阈值特性来研究由Al刻蚀工艺导致的损伤。试验结果表明在阈值Vt漂移中没有发现与天线尺寸相关的损伤,而在栅隧穿漏电流和低源漏电场下亚阈值特性中发现了不同天线比的nMOS器件有相应的等离子充电损伤。在现有的理解上对在RIEAl中nMOS器件等离子充电损伤进行了讨论,并且基于这次试验结果对减小等离子损伤提出了一些建议。     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

A full-process damage detection method using small MOSFET andprotection diode

Short constant voltage stress was applied to the gate of triple metal process transistors to uncover otherwise undetectable process-induced damage, 1 s at 9 MV/cm was enough to distinguish the damaged devices from the undamaged ones clearly in the transistor characteristics. The process damage was detected even after forming gas anneal and without using large antenna test structures to gather the charges. Also, the small diode provided a good leakage path to protect the gate from plasma process induced charging even in the reverse polarity. Diode-protected devices can be used as references in this damage detection scheme     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Effect of CF/sub 4/ plasma pretreatment on low temperature oxides

This study describes a novel technique for forming low temperature oxides (<350/spl deg/C) using a replacement metal gate process. Low temperature oxides were generated by N/sub 2/O plasma in a PECVD system with pretreatment in CF/sub 4/. Fabricated oxides demonstrate excellent current-voltage (I-V) characteristics, such as low leakage current, high breakdown charge and good reliability. Experimental results indicate that CF/sub 4/ plasma treatment can significantly improve the mobility and resistance against hot carrier stress of MOSFETs. With excellent electrical properties, this technique is suitable for fabrication low temperature devices.     

Physical analysis of hard and soft breakdown failures in ultrathin gate oxides

The physical analysis of the ultrathin gate oxides (33 and 25 Å) after the electrical stressing, under constant voltage stress, reveals that the damage is not only limited to the oxide layer, but also to the entire gate structure. The hard breakdown failure makes catastrophic damage to the structure, whereas the analysis of soft breakdown failure reveals many of the hidden damages in the device structure. In Ti-silicided structures, the predominant failure mechanism is Ti migration to form a leakage path, as well as localized re-crystallisation of poly-Si or Si substrate near to the gate oxide. Co migration is so far not seen in Co-silicided devices. However, even for the very low current compliance levels and devices which do not show any electrical degradation after the SBD stress, localized epitaxy formation in the gate or Si substrate is observed, which could be a reliability concern.     

Hf-doped and NH/sub 3/-nitrided high-K gate dielectric thin film with least drain current degradation and flatband voltage shift

A novel technique to form high-K dielectric of HfSiON by doping base oxide with Hf and nitridation with NH/sub 3/, sequentially, is proposed. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared with conventional SiO/sub 2/ gate at the approximately same equivalent oxide thickness. Additionally, negligible flatband voltage shift is achieved with this technique. Time-dependent dielectric breakdown tests indicate that the lifetime of HfSiON is longer than 10 years at V/sub dd/=2 V.     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

Plasma charging damage during contact hole etch in high-density plasma etcher

Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler–Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully.     

The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.     

Gate field emission induced breakdown in power SiC MESFETs

The breakdown mechanism of SiC MESFETs has been analyzed by careful investigation of gate leakage current characteristics. It is proposed that gate current-induced avalanche breakdown, rather than drain avalanche breakdown, is the dominant failure mechanism for SiC MESFETs: thermionic-field emission and field emission are dominant for the ON state (above pinch-off voltage) and the OFF state (below pinch-off voltage), respectively. The effect of Si/sub 3/N/sub 4/ passivation on breakdown voltage has been also investigated. Si/sub 3/N/sub 4/ passivation decreases the breakdown voltage due to higher electric field at the gate edge compared to edge fields before passivation. A reduction in surface trapping effects after passivation results in the higher electric field because the depletion region formed by trapped electrons is reduced significantly.     

High-performance E-mode AlGaN/GaN HEMTs

Enhancement-mode AlGaN/GaN high electron-mobility transistors have been fabricated with a gate length of 160 nm. The use of gate recess combined with a fluorine-based surface treatment under the gate produced devices with a threshold voltage of +0.1 V. The combination of very high transconductance (> 400 mS/mm) and low gate leakage allows unprecedented output current levels in excess of 1.2 A/mm. The small signal performance of these enhancement-mode devices shows a record current cutoff frequency (f/sub T/) of 85 GHz and a power gain cutoff frequency (f/sub max/) of 150 GHz.     

Correlation between two time-dependent dielectric breakdownmeasurements for the gate oxides damaged by plasma processing

The relationship between two time-dependent dielectric breakdown (TDDB), the charge-to-breakdown under constant-current injection (Q_bd), and the time-to-breakdown under constant-voltage stress (t_bd) is derived from a defect generation model and investigated for the gate oxide damaged by plasma processing such as the antenna effect. It is found that although the Q_bd of the damaged oxide monotonously decreases with antenna ratio (r=exposed antenna surface area/gate area), the t_bd does not apparently decrease in a certain antenna ratio region. The difference between the degradation rate of Q_bd and t_bd along r is explained by taking into account the r- and time dependence of gate current density under constant-voltage stress J and the rand J-dependence of Q_bd