A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

A 10 Gb/s hybrid-integrated receiver array module using a planarlightwave circuit (PLC) platform including a novel assembly regionstructure

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

基于XSBI的10Gb/s光纤通信系统的设计(本期优秀论文)

光纤通信凭借其通信容量大、中继距离长、保密性能好、适应能力强等诸多优点在数据通信方面得到了广泛的应用.而单波长10Gb/s的SDH传输平台,代表着当今实用光通信设备的最高水平,文章提出了一种基于XSBI接口协议的10Gb/s光纤通信系统的设计方案,使用FPGA和编解码芯片使以往复杂、高成本的高速光纤通信系统得到了简化.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2$^{11}-$1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.      

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10^-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.     

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns     

Recent Advances in Ultrahigh Bit Rate ETDM Transmission Systems

Increase of Internet traffic and introduction of triple-play services force operators to increase network capacity at moderate costs. Introduction of higher electronic time-division multiplexing (ETDM) channel bit rate targets reduce the cost per bit for the transmission due to lower power consumption, smaller footprint, less management effort, and complexity of the systems. Improved performance of electronic and optoelectronic components allows for research on ETDM bit rates beyond 40 Gb/s, which is currently the highest standardized channel bit rate for optical telecommunication networks. In this paper, an overview of recent progress in high-speed ETDM technology for 80 Gb/s and beyond and results of high-speed ETDM transmission experiments are given. Currently, the speed of electronics enables ETDM systems with line rates of 80/85 Gb/s and even 100 Gb/s, which is expected to be the next generation of Ethernet in data communication     

2.5Gb/s Ethernet over SDH映射芯片实现

设计了一种千兆以太网到2.5Gb/s SDH映射的专用芯片,兼容GFP、ITU-T X.86/Y.1323和HDLC标准.采用双向4路总线流水线结构,77.76MHz的系统时钟,即可全双工处理以太网到2.5Gb/s SDH的实时映射功能.采用TSMC 0.1 3μm工艺流片,技术指标符合ITU-T标准.芯片规模约800万门,满足光纤通信传输的要求,并已成功用于光纤通信设备.     

Planar lightwave circuit platform with coplanar waveguide foropto-electronic hybrid integration

We propose a planar lightwave circuit (PLC) platform constructed on a silica-on-terraced-silicon (STS) substrate for opto-electronic hybrid integration. This platform consists of an embedded silica PLC region, a terraced silicon region for optical device assembly, and a high-speed electrical circuit region. In the electrical circuit region, the coplanar waveguides (CPW) are prepared on a thick-silica/silicon substrate. This structure reduces the propagation loss of the CPW drastically to 2.7 dB/cm at 10 GHz, because the loss tangent (tan δ) of the dielectric constants of silica is much smaller than that of silicon. In order to study the feasibility of this PLC-platform for multi-gigabit operation, we used it to fabricate an LD module in which an LD chip and LD-driver integrated circuits (IC) are assembled on the PLC-platform. A bit error rate measurement of this LD module in a 2.5 Gb/s NRZ showed that this platform is applicable to multi-gigabit optical signal processing     

一种高速数据接口的设计方法

数字通信业务的蓬勃发展对核心元器件的接口带宽提出了越来越高的要求。目前主流元器件解决方案中,主要采用高速串行接口（SerDes）和低压差分接口LVDS实现,但SerDes接口IP价格昂贵。提出一种采用纯数字的采样时钟相位调整和字调整方式,可对源同步数据进行准确采样和恢复,可替代SerDes接口实现10Gb／s16通道LVDS高速接口。本设计方法不依赖于具体的集成电路生产工艺,所使用的IP核是国内主流芯片厂商的主流工艺上都可提供的,可以较低的成本在ASIC芯片上实现高速数据传输接口,满足芯片国产化需求。     

Is 25 Gb/s On-Board Signaling Viable?

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.      

InP DHBT technology and design methodology for high-bit-rateoptical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions     

基于MIMO构架的光OFDM系统研究

文章在分析无线正交频分复用(OFDM)技术和单模光纤偏振特性的基础上,研究了一种基于多输入多输出(MIMO)框架的光OFDM系统并搭建了实验平台.系统将两路12 Gb/sOFDM信号通过偏振复用为24 Gb/s信号,实现了两路信号的解调输出.实验证明,该系统可扩展光纤信道中的频谱划分,增大信道容量,具有较强的对抗光纤色散的能力.     

2.5Gb/s SDH/SONET指针处理器芯片实现

提出了一种2.5Gb/s同步光纤网络SDH/SONET中指针处理器芯片实现结构.指针处理器执行指针解释、通路开销性能监测功能,产生新的与系统时钟同步的STM/STS帧.指针解释模块对输入STM/STS通道的H1/H2指针进行解释,支持48通道的指针解释和每个通道的通路开销监测.采用4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.采用TSMC 0.13μm工艺流片,技术指标符合ITU-T标准.     

基于PC/104的多CAN-Bus系统设计

设计了一种以PC/104为平台、以CAN-Bus为通讯方式来构建功能强大、复杂系统时的解决方案.详细介绍了PC/104的I/O端口和中断等资源;给出如何利用CPLD对CAN接口器件进行控制,以及对整个系统进行编程.