A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

1/spl times/2 and 1/spl times/4 electrooptic switches

We describe the design, fabrication, and testing of two packaged electrooptic switches built from poled LiTaO/sub 3/ crystals. The 1/spl times/2 switch requires a driving voltage of 1200 V and exhibits insertion loss of 2.4 dB and crosstalk of -39.2 dB; the 1/spl times/4 switch exhibits insertion loss and crosstalk of 2.8 dB and -40.6 dB, respectively, and operates using a 1100-V voltage source. The maximum deflection time between the channels is 86 ns.     

A 60-GHz uniplanar MMIC 4/spl times/ subharmonic mixer

A uniplanar GaAs monolithic microwave integrated circuit /spl times/4 subharmonic mixer (SHM) has been fabricated for 60-GHz-band applications using an antiparallel diode pair in finite ground coplanar (FGC) waveguide technology. This mixer is designed to operate at an RF of 58.5-60.5 GHz, an IF of 1.5-2.5 GHz, and an LO frequency of 14-14.5 GHz. FGC transmission-line structures used in the mixer implementation were fully characterized using full-wave electromagnetic simulations and on-wafer measurements. Of several mixer configurations tested, the best results show a maximum conversion loss of 13.2 dB over the specified frequency range with a minimum local-oscillator power of 3 dBm. The minimum upper sideband conversion loss is 11.3 dB at an RF of 58.5 GHz and an IF of 2.5 GHz. This represents excellent performance for a 4/spl times/ SHM operating at 60 GHz.     

New radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithms for 3-D DFT

In this paper, new three-dimensional (3-D) radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithms are developed and their implementation schemes discussed. The algorithms are developed by introducing the radix-2/4 and radix-2/8 approaches in the computation of the 3-D DFT using the Kronecker product and appropriate index mappings. The butterflies of the proposed algorithms are characterized by simple closed-form expressions facilitating easy software or hardware implementations of the algorithms. Comparisons between the proposed algorithms and the existing 3-D radix-(2/spl times/2/spl times/2) FFT algorithm are carried out showing that significant savings in terms of the number of arithmetic operations, data transfers, and twiddle factor evaluations or accesses to the lookup table can be achieved using the radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) DIF FFT algorithm over the radix-(2/spl times/2/spl times/2) FFT algorithm. It is also established that further savings can be achieved by using the radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithm.     

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB/spl Omega/ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.     

A low-power PLA for a signal processor

A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70°C indicate that the circuit works as expected in a range extending to at least 3.5 V     

A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.     

A small OCA on a 1/spl times/0.5-mm/sup 2/ 2.45-GHz RFID Tag-design and integration based on a CMOS-compatible manufacturing technology

This letter reports, for the first time, on the design strategy and process integration for a small on-chip-antenna (OCA) with a radio-frequency identification (RFID) tag chip-area /spl sim/1/spl times/0.5 mm/sup 2/. It is designed based on a 2.45-GHz RFID tag circuit with an inductive-coupling model. A patterned Al shielding layer is used to improve the consistency of the actual performance obtained from fabricated devices and those predicated from the design. The antenna's inductor coils were fabricated based on a conventional Cu-Damascene process. To achieve the required antenna performance (e.g., Q-factor), a set of thick USG and deep-via etch processes were specifically developed. Our results demonstrate that the dc power converted by the OCA is sufficient to enable the RFID tag chip to communicate with a corresponding 2.45-GHz RFID reader with a 1-mm distance.     

Low-loss singlemode fibre 1/spl times/2 Y-junction

A new method for the fabrication of a singlemode fibre wavelength independent Y-junction is described; through asymmetrically tapering a pre-assembled Y-junction precursor, the splice point is drawn into the waist region of the device and low-loss is ensured. The lowest loss and flattest wavelength response for such a device is reported.     

A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.     

A 2/spl times/2 antennas Bluetooth system

This paper presents a new space-time FSK coding scheme suited for non coherent MIMO systems. These codes keep the natural advantages of the FSK modulations and achieve full diversity and high spectral efficiency. This coding scheme can be easily adapted to Bluetooth. We propose a 2/spl times/2 antennas Bluetooth FSK system that doubles the data rate and improves the performance.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

An electrostatically actuated 1/spl times/2 moving-fiber switch

A 1/spl times/2 moving-fiber switch for optical protection switching is presented. A detailed measurement of the optical performance is given. A coupling loss of 0.5 dB is achieved in the lensless optical path based on butt-coupled standard single-mode fibers. The actuation voltage is approximately 30 V. Both the electrostatic parallel-plate actuators and the fiber alignment structures are realized by anisotropic machining of crystalline silicon. This type of switch is designed for compact rows of switches.     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

A low-power 2/5.8-GHz dual-wide-band CMOS LC-VCO with switched-inductor technique

A fully integrated dual-band LC voltage control oscillator, designed in a 0.18-µm CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications, is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38–6.23?GHz and 1.78–2.07?GHz with 15% frequency tuning range. Two different inductors are used for the frequency band switching. Frequency tuning is implemented by varying the capacitance of a MOS varactor. The measured phase noise is ?109?dBc/Hz @ 1?MHz and ?112?dBc/Hz @ 1?MHz for frequency at 5.8?GHz and 2?GHz, respectively. This oscillator is fabricated in UMC's 0.18-µm one-poly-six-metal 1.8?V process. The power dissipation of this dual-band VCO is 11.7 and 9.3?mW for oscillation frequency of 2?GHz and 5.8?GHz, respectively.     

A low-power 1-GHz super-regenerative transceiver with time-sharedPLL control

A low-power transceiver for ISM applications in the 868-MHz band has been integrated in a 0.8-μm BiCMOS technology. The receiver part is based on the super-regenerative principle. The system includes two time-shared control loops, one for the selectivity and sensitivity control and one for the frequency control (PLL). The receiver with its PLL draws 3.6 mW for a sensitivity of -105 dBm and the emitter current consumption is 6 mA for a 0-dBm output power. A 2.4-V operation voltage allow the use of a two-batteries solution     

Characterization of 1/spl times/N broadcast and 2/spl times/N multicast packet switching using active-vertical-coupler-based optical crosspoint switch

This paper reports the expansion of a novel optical multicast scheme to 1-to-4 and 2-to-4 configurations using an active-vertical-coupler (AVC)-based optical crosspoint switch (OXS) matrix. A 1-to-4 broadcast experiment has been carried out first, with only 0.5 dB excess loss per signal split. Input signals with two wavelengths are then fed into one row of OXS to investigate the effect of wavelength-division multiplexing on the 1-to-4 multicast switching. Finally, combining both, the expanded 2-to-N multicast is also achieved with an N value up to 4. The switching characteristics, switched signal quality, and optical signal-to-noise ratio (OSNR) have been investigated in different configurations. Power penalties of less than 4.5 dB are found in worst case switched signals in the 2-to-4 configuration. Slow OSNR degradation in line with previous prediction is also observed. The measured results confirm the excellent multicast switching characteristics nearly free from power splitting loss in this device.     

A thin-film filter-based 1/spl times/2 reconfigurable fiber-optic add-drop module with a quadruple fiber-optic collimator

Due to a limited optical crosstalk in most thin-film filter (TF)-based fiber-optic modules, we propose and experimentally verify a low optical crosstalk TF-based 1/spl times/2 reconfigurable fiber-optic add-drop structure. Our key idea is to employ a passive noise rejection scheme by introducing a double reflection on the TF as well as a spatial separation through a combination of a quadruple and a single fiber-optic collimators. Our experimental results show a much improved <-39.1-dB optical crosstalk at the Thru port. In addition, the measured average optical losses at the Drop and the Thru ports are 1.40 and 1.23 dB, respectively, when the TF is in the optical path. When the mirror is in the optical path, all wavelength optical beams are directed to the Thru port with a measured average 2.50-dB optical loss. A low polarization-dependent loss of <0.17 dB is also determined. Furthermore, our design concept can be used to form a low optical crosstalk fixed three-port add-drop filter and a high dynamic-range wavelength-sensitive variable fiber-optic attenuator.     

Micromachined 1/spl times/n fiber-optic switch

A new microfabrication technology based on bulk anisotropic etching is presented that offers significant improvements over present microoptical and microphotonic devices. With this new technology we have fabricated 200 /spl mu/m to 2 cm translational stages, fiber-to-fiber couplers, and fiber-to-planar waveguide couplers. In this letter we present the fabrication and characterization of a 1/spl times/n micromechanical fiber-optical switch. The nonoptimized devices show switching times <10 ms with <-1-dB loss. Significant improvements in both parameters appear possible with future refinements. The devices are simple to fabricate, compact, and show considerable promise in the future of fiber-optic networks. Actuation of the switch is accomplished magnetically although other actuation mechanisms are also possible.