A simplified computer analysis for n-well guard ring efficiency in CMOS circuits

Based on solving the 2-D continuity and current transport equations for electrons injected into the substrate of a n-well CMOS, a quantitative evaluation of n-well guard ring efficiency in terms of the escape electron current is presented. Simulation results show that in the worst-case condition Auger recombination inherent in the heavily-doped substrate of epi-CMOS is responsible for the enhancement of n-well guard ring efficiency. Also, our simulations show that the substrate doping should be as high as possible and the epi-layer thickness should be as thin as possible. Thus a narrow well-type guard ring can be used in order to make efficient use of epi-CMOS for suppressing the escape electron current to a low level so as to preclude latch-up.     

Epitaxial layer enhancement of n-well guard rings for CMOS circuits

n-well guard rings have long been used for isolating potential electron injectors to avoid latch-up of CMOS circuits. Such guard rings are shown to be orders of magnitude more efficient for CMOS fabricated in an epitaxial layer (epi-CMOS) than for bulk (non-epi) CMOS. The maximum escape probability in epi-CMOS measures 3.9E-06 while for bulk CMOS it is 1.8E-02.     

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n⁺-p⁺ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm     

Resistance modulation effect in n-well CMOS

The characteristics of n-well CMOS latchup have been measured and quantitatively analyzed. It was found that the resistance of the substrate and of the well modulated by minority-carrier injection from the emitter of the parasitic bipolar transistors, and that the latchup trigger current was about two times larger than that calculated without the modulation. It was also confirmed that the holding current level is well explained if the modulation effect is brought into consideration. The latchup analysis with the modulation effects should give useful information for optimizing the structure and concentration of the well and the substrate.     

Vertical isolation in shallow n-well CMOS circuits

This letter examines vertical punchthrough in a shallow conventional n-well suitable for use in high-packing-density VLSI CMOS circuits. It is shown that full vertical isolation can be maintained even when the well beneath a p+ diffusion is completely depleted-that is the p+-to-n-well and n-well-to-p-substrate depletion regions meet-and that this offers an advantage in terms of p+ junction capacitance. However, if thin p-on-p+ epitaxial substrate material is used for latch-up suppression, then vertical isolation can be severely degraded. This effect ultimately limits the thickness of the epitaxial layer and hence the degree of latch-up protection.     

An analytic model of holding voltage for latch-up in epitaxial CMOS

For epitaxial CMOS in the latched state, the region between the anode and the cathode is conductivity modulated. In this case, the two-transistor model for the silicon-controlled rectifier (SCR) is not valid. However, a simplified analysis is possible because the well-substrate junction is obliterated by carriers. With this approach an analytic model is developed which can predict the holding voltage and its dependence on design parameters. The model is capable of predicting quantitatively the improvement in holding voltage with increased n+ -to-p+ spacing, thinner epi, substrate backbias, shallow trench, and silicided junctions and higher epi doping. The model explains a previously observed scaling law for the holding voltage.     

Latchup performance of retrograde and conventional n-well CMOS technologies

The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p⁺epitaxial material.     

An isolated vertical n-p-n transistor in an n-well CMOS process

Isolated vertical n-p-n transistors were fabricated by a modified 5-/spl mu/m n-well CMOS process. The modification included a decrease in the p/SUP +/ source and drain implant dose and an increase in the final anneal time, but no extra processing steps of masks were required. The n-p-n transistors had generally good characteristics, with H/SUB FE//spl ap/600 and BV/SUB CEO//spl ap/40 V, while the MOS characteristics were unchanged.     

Dramatic reduction of optical crosstalk in deep-submicrometer CMOS imager with air gap guard ring

A dielectric structure, air gap guard ring, has been successfully developed to reduce optical crosstalk thus improving pixel sensitivity of CMOS image sensor with 0.18-/spl mu/m technology. Based on refraction index (RI) differences between dielectric films (RI = 1.4 /spl sim/ 1.6) and air gap (RI = 1), total internal reflection occurred at dielectric-film/air-gap interface, thus the incident light is concentrated in selected pixel. Excellent optical performances have been demonstrated in 3.0 /spl times/ 3.0 /spl mu/m pixel. Optical spatial crosstalk achieves 80% reduction at 20/spl deg/ incidence angle and significantly alleviates the pixel sensitivity degradation with larger angle of incident light.     

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 μm AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

A physical model for the correlation between holding voltage andholding current in epitaxial CMOS latch-up

A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings. This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined     

A model for n-well junction effect on gate-charging damage inPMOSFETs

A quantitative model explaining N-well junction effect on gate charging damage in PMOSFETs is presented. This model takes into account the reverse-biased N-well junction leakage, generated both thermally and by photons and its behavior on limiting charging current passing through gate oxide during plasma processing. The modeling results suggest that plasma illumination plays a key role in enabling gate charging damage in PMOSFETs. The model can also apply to reverse-biased source and drain junctions in both P and NMOSFETs during plasma events     

Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies

The goal of this paper is to provide some useful design guidelines at the device level regarding the main challenges to be typically faced in the design and integration of Geiger-mode avalanche diodes in a standard CMOS process. Different techniques are found in literature in order to avoid premature edge breakdown with the aim of limiting the electric field at the edges to be weaker than in the multiplication region. In this article, the use of such techniques, the conditions where they can effectively work and above all their limitations are studied by means of TCAD simulations for various diode architectures. Additionally, the noise performance is discussed by focusing on the band-to-band tunneling and shallow trench isolation enhanced dark count rates. Geiger-mode bias techniques as well as a synthesis on the pros and cons of the various avalanche diode architectures are finally presented aiming at facilitating future design choices.     

Design guidelines of actively mode-locked fiber ring lasers

This letter presents guidelines of how to design actively mode-locked fiber ring lasers to generate nearly transform-limited soliton pulses. The minimum fiber cavity length and/or dispersion, with which nearly transform-limited soliton pulses can be generated, need to satisfy an additional condition besides two previously known conditions of stability     

Design of efficient CMOS ring oscillator-based random number generator

Although studies have investigated the effects of flicker noise on randomness, such effects demand further examination. Despite the random nature of flicker noise, a coloured distribution is observed in the power spectral density of flicker noise, indicating to a correlation in between adjacent samples. Studies have employed ring oscillators (ROs) that produce random numbers by sampling the digitised analogue signals of their outputs. This sampling procedure may change the spectral properties of flicker noise resulting from the folding effect of noise. Another topic of interest regarding sampled flicker noise is its random behaviour. To investigate the contribution of flicker noise, white noise, and their combination to randomness, we produce synthetic bit streams of these noise sources. From observations, we find that flicker noise contributes to the entropy of bit streams. Using the generated synthetic bit streams, we also explore the entropy dependence of a bit stream on the sampling period and analyse and compare the entropy levels of the outputs of ROs operating in strong and weak inversion. Results of the comparison demonstrate that only one RO operating in weak inversion may be sufficient to attain the required entropy level for qualifying the generated bit stream as random. The results of the analysis are also confirmed by measurements. In addition, the paper proposes an efficient design of a RO-based random number generator.     

Application of selective silicon epitaxial growth for CMOS technology

The application of selective silicon epitaxial growth for device isolation is described. An improved selective epitaxial isolation technology is presented in the fabrication of CMOS LSI. This advanced process technology results from a superior selectivity for selective silicon deposition. A CMOS ring oscillator with a twin-well structure is fabricated by using this selective epitaxial isolation technology. The feasibility of using an oversized contact, due to the nature of its steeper oxide-to-silicon isolation boundary, is demonstrated.     

Hot-carrier-reliability design guidelines for CMOS logic circuits

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft_rise and 10/ft_fall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively     

Design guidelines of CMOS class-AB output stages: a tutorial

This article presents useful guidelines for designing CMOS class-AB output stages. Three Quality Factors, which allow analysis and comparison of different output stages, are used to design two CMOS class-AB stages. We show that using the proposed Quality Factors and the related strategy leads to an efficient design in terms trade-off among area, current consumption, bandwidth and distortion. Indeed, for one of the two stages adopted as example, the design through the Quality Factors results in superior distortion performance with respect to the design suggested in the original article. Design examples and simulations are provided to validate the design strategy.     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.