一种用于带通Σ-Δ调制器的25MHz低功耗开关电容谐振器

介绍了一种运用于带通Σ-Δ调制器的谐振频率为25MHz的低功耗开关电容DD谐振器电路.电路采用了运算放大器共享技术和双采样技术,同时对单元电路进行优化,达到功耗最小化.该谐振器电路采用SMIC 0.25μm混合信号CMOS工艺进行设计,整个电路模块面积仅为0.09mm2.测试结果表明,使用该谐振器电路的带通Σ-Δ调制器工作于100MHz采样频率时,对于信号带宽为1kHz的输入信号,调制器的输出在谐振频率处SFDR约为77dB.整个谐振器功耗为10.5mW.     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

2.2MHz,8.3mW多位量化连续时间Sigma-Delta调制器设计

本设计完成了一款2.2MHz、8.3mW连续时间Sigma-delta调制器,可应用于无线通信领域.与传统的离散结构相比,连续结构在实现兆赫兹以上带宽的同时,显著降低了功耗,并且在低电源电压下也有很好的发展潜力.此Sigma-delta调制器采用前馈单环三阶四位量化结构,考虑了非零环路延时效应,设计了补偿网络.在标准0.18μm CMOS工艺下,完成了调制器电路的设计.经过Cadence Spectre仿真验证,调制器的信号带宽为2.2MHz,动态范围为69dB,在1.8V电源电压下,电路总功耗仅为8.3mW.     

一种前馈架构的Σ-Δ调制器设计

基于40 nm CMOS工艺,设计了一种前馈架构的3阶1位量化离散时间Σ-Δ调制器。该调制器的信号带宽为100 kHz,过采样比为128。为了适应低电压环境,输入端开关采用栅压自举结构以提升采样信号的线性度,运算放大器采用两级结构以增加输出摆幅。为了降低系统功耗,比较器采用动态结构实现。仿真结果表明,在1.2 V电源电压下,该调制器的最高信噪比为88.1 dB,功耗为1.5 mW。     

低功耗Sigma Delta调制器的建模与设计

针对Sigma Delta ADC在实现高精度的同时如何降低系统功耗这一问题,通过进行建模分析,得出满足精度需求的最低性能指标。并对二阶Sigma Delta调制器的非理想因素进行数学建模分析,在满足ADC精度的同时对ADC组成模块的最低性能指标进行分配,利用SDtoolbox进行仿真验证。基于CSMC 0.5 μmCMOS工艺,在5 V电源电压下,对调制器进行了电路级设计。结果显示在模块最低性能时,调制器输出信号的带内信噪比为835 dB,总功耗为18 mW。     

一种采用斩波一稳零技术的低功耗Delta—Sigma调制器的设计

采用TSMC0．18μm CMOS混合信号1P6M工艺实现了一种应用于信号检测系统的低功耗Delta--Sigma调制器．该调制器采用单环积分器级联反馈（CIFB）结构降低了电路的复杂度,并采用Chopper-Stabilization技术降低了系统的直流失调和1／f噪声,提高了电路的低频特性．调制器采用1．8V电源电压,整体功耗仅为2mW,版图尺寸1．25×1．3mm^2．仿真结果表明,该调制器在50kHz信号带宽范围内,可以达到92dB的信噪失真比,99．3dB的动态范围和15bits的有效位数,满足传感器信号检测系统的要求．     

基于开关电容技术的Σ-Δ调制器的设计

基于0.18μm标准CMOS工艺,设计并实现了一个单环三阶开关电容Σ-Δ调制器。电路采用具有加权前馈求和网络的积分器级联型拓扑结构,采用优化的具有正反馈的单级A类OTA来降低功耗。在设计中,采用电流优化技术来降低运算跨导放大器(OTA)的功耗。Σ-Δ调制器的过采样率为128,时钟频率为6.144 MHz,信号带宽为24 kHz,最大信噪比为100 dB,动态范围为103 dB。电路在1.8 V电源供电下功耗为2.87 mW。     

一种低电压3阶4位前馈Σ-Δ调制器

介绍了一种应用于无线通信领域的低电压、带有前馈结构的3阶4位单环Σ-Δ调制器。为了降低Σ-Δ调制器的功耗,跨导放大器采用了带宽展宽技术。采用TSMC 0.13 μm CMOS工艺对电路进行仿真,仿真结果显示,当工作电压为1.2 V、采样频率为64 MHz、过采样比为16、信号带宽为2 MHz时,电路的SNDR达81 dB,功耗仅为7.78 mW。     

面向石墨烯霍尔器件检测应用的模拟前端电路

面向石墨烯霍尔器件的检测应用,设计了一款斩波稳定的模拟前端电路。基于可编程斩波放大器和2阶斩波Σ-Δ调制器进行设计,获得了良好的噪声性能和较大的输出动态范围。采用SMIC 0.18 μm 1P6M混合信号工艺实现,电路整体面积为1.84 mm²。测试结果表明,在电源电压为3.3 V,信号带宽为50 Hz条件下,该模拟前端电路的典型输出信号失真比达到58.4 dB,有效精度为9.4 位,整体功耗仅为1.32 mW,磁场检测分辨率可达4.4×10-5 T。     

一种满摆幅输入的高精度Σ-Δ调制器设计

针对高精度 Σ-Δ 调制器因采用高阶或者级联结构而存在满摆幅输入条件下积分器容易过载以及电路复杂度较高的问题,利用Matlab设计了一种满摆幅输入的高精度 Σ-Δ 调制器。采用描述调制器时域模型的方法,使用代码自动综合出满足要求的调制器系数。该调制器电路采用Tower Jazz 0.18 μm CMOS工艺进行设计与仿真,结果表明,带宽内的信噪失真比达到105.5 dB,有效位数为17.2位,版图面积为0.4 mm2,在5 V电源电压下功耗为1.2 mW。该调制器可用于对任意输入信号幅度的低频微弱信号进行精确检测的传感器信号采集电路中。     

A 65-nm low-noise low-costΣ△modulator for audio applications

正This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio(SNDR) and 105 dB dynamic range(DR) over the 22.05-kHz audio band and occupies 0.16 mm~2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.     

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

The design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.     

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulatorin CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1_mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1_single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four     

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections     

16-Bit三阶级联结构Sigma—Delta调制器的设计

设计一款可应用于压力传感器的高精度三阶2—1级联结构Sigma—delta调制器。MatlabSimulink建模仿真表明,信号带宽为500Hz,过采样率为128的情况下,该调制器信噪比高达119dB。通过对调制器非理想因数的分析,采用典型的0．35μm工艺整体实现该调制器,并用Spectre仿真,电路信噪比可达106．2dB,高于16住要求的98dB,整个调制器的功耗约为7mW。