Investigation of the underfill delamination and cracking inflip-chip modules under temperature cyclic loading

In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Reliability study of package-on-package stacking assembly under vibration loading

The vibration reliability of lead-free solder joints of Package-on-Package (PoP) is investigated by experimental tests and finite element method (FEM) simulations in this paper. A 14 × 14 mm two-tier PoP module was selected for this study. The natural frequencies and modes were determined by FEM and verified by experimental tests. The printed circuit board (PCB) assemblies are tested under harmonic vibration. Vibration test results show that the vibration reliability of top package is better than the bottom package, and the outermost corner solder joints of the bottom package are the critical solder joints for the PoP under vibration loading. The stress characteristics of solder joints obtained by FEM are well correlated with the experimental results. Failure mechanism analysis indicates that the bottom solder joints become the most vulnerable part of the PoP under vibration due to the bigger relative displacements between the PCB and the bottom package. The micro-structural analysis indicates that cracks usually originate in the bottleneck position of the solder balls, extend within bulk solder and then propagate along the interface between the IMC layer and the bulk solder. The influence of bottom solder joints standoff for vibration reliability was analyzed by FEM as well. Results show that the higher the bottom solder joints' standoff, the more difficult the failure for the PoP assembly.     

Reliability study of board-level lead-free interconnections under sequential thermal cycling and drop impact

The sequential thermal cycling (TC) and drop impact test are more reasonable to evaluate the reliability of lead-free solder interconnections compared with separate TC test or drop impact test. In this paper, sequential TC (−40 °C/125 °C, 13 min of soak time, 12 min of dwell time, totally 50 min of cycle time) and drop impact test (a sine impact pulse with a peak acceleration of 1500g and a duration time of 0.5 ms) were conducted to study the failure mechanism of solder interconnections under sequential TC and drop impact test. The TC load has larger effect on the Cu/solder interface at the PCB side than that of Ni (P)/solder interface at the component side. For the thermally cycled samples, the failure location of solder interconnections under drop impact has changed from initiation and propagation along the thin reaction layer (mode 1) between intermetallic compound (IMC) layer and Ni (P) pad at the component side to initiation at the bulk solder and propagation along the Cu₃Sn IMC layer (mode 2) or entirely through the bulk solder (mode 3) at the PCB side. The failure mechanism has also changed from the entirely brittle crack to the mixture of fatigue crack and brittle crack.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

用高低温循环加速试验评估光源模块长期贮存寿命的研究

Light source modules are the most crucial and fragile devices that affect the life and reliability of the interferometric fiber optic gyroscope （IFOG）. While the light emitting chips were stable in most cases, the module packaging proved to be less satisfactory. In long-term storage or the working environment, the ambient temperature changes constantly and thus the packaging and coupling performance of light source modules are more likely to degrade slowly due to different materials with different coefficients of thermal expansion in the bonding interface. A constant temperature accelerated life test cannot evaluate the impact of temperature variation on the performance of a module package, so the temperature cycling accelerated life test was studied. The main failure mechanism affecting light source modules is package failure due to solder fatigue failure including a fiber coupling shift, loss of cooling efficiency and thermal resistor degradation, so the Norris-Landzberg model was used to model solder fatigue life and determine the activation energy related to solder fatigue failure mechanism. By analyzing the test data, activation energy was determined and then the mean life of light source modules in different storage environments with a continuously changing temperature was simulated, which has provided direct reference data for the storage life prediction of IFOG.     

Reliability analysis of UHF RFID tags under long-term mechanical cycling

Radio Frequency Identification is becoming more and more popular although unit price of RFID tags is still higher than price of barcodes. Further decrease in cost of using RFID techniques can be possible to achieve by recycling of tags. However, their multiple use causes that RFID tags are placed repeatedly on a surface of identified object and then, peeled off. Thus, tags have to withstand even long-term mechanical exposure in order to guarantee reliable work in a long period of time. In this paper, reliability of UHF tags under long-term mechanical cycling is reported. Two different RFID tags were used to perform investigations which revealed that mechanical properties of tested RFID tags are mostly dependent on their stackup, i.e. additional top and internal foil or paper layers may introduce significant growth of mechanical durability of the tested RFID tag samples.     

Effect of glue on reliability of flip chip BGA packages under thermal cycling

Glue is widely used to improve the reliability of ball grid array (BGA) under mechanical shock and vibration. Although it has been demonstrated to have a positive effect on the reliability of BGA under mechanical impact, it can have adverse effects on BGA under thermal cycling. This paper investigates the effect of glue on the reliability of BGA under thermal cycling using both experimental and numerical methods. The digital image correlation (DIC) technique was used to obtain the thermal mechanical behavior of the package. The experimental results explain in detail how the glue negatively affects the reliability of the BGA. Furthermore, a finite element analysis was performed and its results were verified with experimental results. A numerical parametric study was carried out on various mechanical properties, configurations of the glue, and introduction of a stiffener using the validated FEM model. The results show that the reliability of BGA strongly depends on geometries and material properties of the glue. Based on the results, a guideline of glue selection for BGA reliability under thermal cycling is formulated.     

Reliability investigation of InGaP/GaAs HBTs under current and temperature stress

The reliability of InGaP/GaAs N–p–n heterojunction bipolar transistors (HBTs) with different base metal contact systems (Au/Zn/Au, Ti/Au, Ti/Pt/Au and the novel Ti/ZrB₂/Au) under current and temperature stress is studied in this paper. We further report results of current stress on three p-GaAs doping impurities namely Zn, Be and C. The effect of O⁺/H⁺ and O⁺/He⁺ ions, used in the fabrication of planar self-aligned HBTs, is also investigated in the stability of device dc current gain. The instability phenomena typical of each factors and their effects on the HBT characteristics are reported.     

Failure mechanisms of lead-free chip scale package interconnections under fast mechanical loading

The reliability of chip scale package (CSP) components against mechanical shocks has been studied by employing statistical, fractographic, and microstructural research methods. The components having high tin (Sn0.2Ag0.4Cu) solder bumps were reflow soldered with the Sn3.8Ag0.7Cu (wt.%) solder paste on Ni(P)|Au- and organic solderability preservative (OSP)-coated multilayer printed wiring boards (PWBs), and the assemblies were subjected to the standard drop test procedure. The statistically significant difference in the reliability performance was observed: the components soldered on Cu|OSP were more reliable than those soldered on Ni(P)|Au. Solder interconnections on the Cu|OSP boards failed at the component side, where cracks propagated through the (Cu,Ni)₆Sn₅ reaction layer, whereas interconnections on the Ni(P)|Au boards failed at the PWB side exhibiting the brittle fracture known also as “black pad.” In the first failure mode, which is not normally observed in thermally cycled assemblies, cracks propagate along the intermetallic layers due to the strong strain-rate hardening of the solder interconnections in drop tests. Owing to strain-rate hardening, the stresses in the solder interconnections increase very rapidly in the corner regions of the interconnections above the fracture strength of the ternary (Cu,Ni)₆Sn₅ phase leading to intermetallic fracture. In addition, because of strain-rate hardening, the recrystallization of the as-soldered microstructure is hindered, and therefore the network of grain boundaries is not available in the bulk solder for cracks to propagate, as occurs during thermal cycling. In the black pad failure mode, cracks nucleate and propagate in the porous NiSnP layer between the columnar two-phase (Ni₃P+Sn) layer and the (Cu,Ni)₆Sn₅ intermetallic layer. The fact that the Ni(P)|Au interconnections fail at the PWB side, even though higher stresses are generated on the component side, underlines the brittle nature of the reaction layer.     

热循环与随机振动加载下电路板的寿命预测

随着电子封装业的快速发展,产品可靠性成为重要研究课题之一,寿命作为可靠性的衡量指标具有参考价值。利用ANSYS,结合有限元理论与寿命预测模型,在热循环与随机振动加载下对装配有典型封装结构的电路板进行响应分析和寿命预测。采用Anand统一本构模型,根据体积加权平均法,选择基于能量的Darveaux模型预测热疲劳寿命。根据Manson经验高周疲劳关系式,结合Miner准则,选择基于高斯分布的Steinberg模型预测振动疲劳寿命。采用线性损伤叠加法得到热与振动同时加载下结构的寿命。结果表明:焊点与Cu引线的连接层易发生破坏。焊点易出现热疲劳失效,Cu引线易出现振动疲劳失效。     

热循环加载片式元器件带空洞无铅焊点的可靠性

建立了片式元器件带空洞无铅焊点有限元分析模型,研究了热循环加载条件下空洞位置和空洞面积对焊点热疲劳寿命的影响.结果表明:热循环加载条件下空洞位置和空洞面积显著影响焊点热疲劳寿命.空洞位置固定于焊点中部且面积分别为7.065×10-4,1.256×10-3,1.963×10-3和2.826×10-3mm2时,焊点热疲劳寿...     

Lifetime of power electronics interconnections in accelerated test conditions: High temperature storage and thermal cycling

We investigate the effect of three testing conditions (thermal shock, Rapid Temperature Change – RTC – and high temperature storage) on the interconnects of a power electronic module. In particular, the mechanical strength of thick aluminium wirebonds is investigated and shows that while it is not affected by storage at 230 °C, it is much more sensitive to thermal cycling. Shock tests are found to be especially severe, despite having a smaller temperature swing than RTC. Regarding the die attach, no noticeable reduction in mechanical strength is found, regardless of the ageing conditions, and despite clear micro-structural evolutions.     

热载荷下金属间化合物厚度对焊点可靠性的影响

研究了在热循环载荷条件下,不同厚度的金属间化合物IMC(Intermetallic Compound)层对焊点可靠性的影响。采用Anand本构模型描述无铅焊点在热载荷条件下的粘塑性力学行为,运用有限元模拟电子封装器件在热载荷循环下的应力应变的变化规律,确定关键焊点的位置,得到关键焊点的关键点的应力、应变与时间关系的曲线,分析IMC层厚度与寿命关系曲线,并确定其函数关系。研究表明:在热载荷条件下IMC层厚度越大,其焊点的可靠性越低,寿命越短。在IMC层厚度为8.5μm时,IMC厚度对焊点寿命的影响率出现明显的变化,影响率由–32.8突然增加到–404,当IMC厚度为14.5μm时,焊点的寿命值出现了跳跃。     

Deformation mechanism and its effect on electrical conductivity of ACF flip chip package under thermal cycling condition: An experimental study

In this study, experimental works are performed to investigate the deformation mechanism and electrical reliability of the anisotropic conductive adhesive film (ACF) joint subjected to temperature cycling for flip chip on organic board (FCOB) assemblies. This paper presents some dominant deformation parameters governing the electrical degradation in an ACF joint between a chip and a substrate when flip chip assembly is heated and cooled. The deformation mechanism of ACF flip chip assemblies during the temperature cycling are investigated using in situ high sensitivity moiré interferometry. A four-point probe method is conducted to measure the real-time contact resistance of ACF joint subjected to the cyclic temperature variation. As the temperature increases below T_g of ACF, the bending displacement of assembly decreases linearly. At the temperature higher than T_g of ACF, there is no further change in bending behavior and in-plane deformations of a chip and a substrate become approximately free thermal expansion. It is because that soft-rubbery ACF at the temperature above T_g cannot provide the mechanical coupling between a chip and a substrate. The effect of bump location on the temperature dependent contact resistance is evident. A characteristic hysteresis in bending curves is observed and discussed. The contact resistance of the corner bumps increases with increasing temperature at a higher rate when compared to that of the middle. Failure analysis is performed to examine the ACF interconnections before and after thermal cycling test. The results indicate that during the thermal loading, the shear deformation is more detrimental to the electrical degradation of ACF joints than normal strain.     

A 4/7 kHz audio bandwidth selectable digital phone interface (DPI)chip with on-chip analog functions and modem

The Digital Phone Interface (DPI) is designed for a new generation of digital telephone terminals for private exchanges, This circuit gives a total solution for all telephone functions, thereby including DSP functions, voice coding/decoding and analog front end, signal generators for DTMF and ringing, a modem for data transfer between terminal and exchange and a multitude of interfaces to communicate to the external world. Besides the normal earpiece micro and speaker, handsfree operation is available by using a selectable input low-noise microphone amplifier and an additional 50 Ω mWLS driver. For the handsfree operation, a digital AGC and anti-oscillation (anti-larsen) function is implemented. The line modem generates a modified RTZ (WAL2) code and is able to cover distances up to 1.5 km. In addition, the component is extensible with external signal processing modules (echo cancelling) and is also able to transfer a 7 kHz speech bandwidth. The device is a mixed analog/digital design produced in a 1.2 μm CMOS technology on 46 mm ² die area and consumes 200 mW     

Degradation of AlInGaP red LEDs under drive current and temperature accelerated life tests

AlInGaP LEDs are widely used in illumination applications as automotive and signalization due their low consumption and high durability. In order to verify the high durability data it is necessary to consider not only catastrophic failures but also degradation. In this work LEDs degradation at different temperature and drive current accelerated tests have been analyzed. In all the tests we have carried out an exponential degradation trend have been observed. Temperature and drive current influence in degradation rate and reliability have been evaluated.     

Failure study of Sn37Pb PBGA solder joints using temperature cycling,random vibration and combined temperature cycling and random vibration tests

In this paper, the tin-lead (Sn-37wt%Pb) eutectic solder joints of plastic ball grid array (PBGA) assemblies are tested using temperature cycling, random vibrations, and combined temperature cycling and vibration loading conditions. The fatigue lives, failure modes for the solder joints and the typical locations of the failed solder joints for single-variable loading and combined loading conditions are compared and analyzed. The results show much earlier solder joint failure for combined loading than that for either temperature cycling or pure vibration loading at room temperature. The primary failure mode is cracking within the bulk solder under temperature cycling, whereas the crack propagation path is along the intermetallic compound (IMC) layer for vibration loading. The solder joints subjected to combined loading exhibit both types of failure modes observed for temperature cycling and vibration loading; in addition, cracking through the IMC and the bulk solder is observed in the combined test. For temperature cycling and vibration loading, the components in the central region of the printed circuit board (PCB) have more failed solder joints than other components, whereas for combined loading, the number of failed solder joints in the components in different locations of the PCB is approximately the same.     

Failure analysis on lattice matched GaInP/Ga(In)As/Ge commercial concentrator solar cells after temperature accelerated life tests

Accelerated life tests are frequently used to provide reliability information in a moderate period of time (weeks or months), and after that, a failure analysis is compulsory to detect the failure origins. In this paper, a failure analysis has been carried out after a temperature accelerated life test on lattice matched GaInP/Ga(In)As/Ge triple junction commercial solar cells. Solar cells were forward biased in darkness inside three climatic chambers in order to emulate the photo‐generated current under nominal working conditions (a concentration level of 820 suns). After the accelerated aging test, a characterization of the resulting cells by means of quantum efficiency, dark and illumination I–V curves, electroluminescence, scanning electron microscope, energy dispersive X‐ray, scanning transmission electron microscope and X‐ray photoelectron spectroscopy has been carried out. Current is identified as the cause of degradation while temperature just dominates the accelerating factor of the aging test. Current promotes the front metal damage produced by the chemical evolution of the electroplating impurities together with those of the tab soldering process. Semiconductor structure does not seem to be responsible of any failure. Therefore, this kind of lattice matched GaInP/Ga(In)As/Ge triple junction solar cells, that as of 2016, are the workhorse of CPV technology, exhibits as a very robust device if the front metal connection is properly accomplished. Copyright © 2016 John Wiley & Sons, Ltd.     

Computer study of phosphorus segregation mechanisms at a SiO2/Si(100) interface

Phosphorus is shown to segregate both at a perfect SiO₂/Si(100) interface and at an interface with defects. Depending on the particular mechanism of segregation (substitution for isolated silicon atoms near the interface, attraction to vacancies and self-interstitial silicon atoms accumulated near the interface, etc.), the segregation energy can vary from 0.5 to 1.0 eV. At high concentrations of defects (comparable with that of silicon atoms), the segregation energy decreases to 0.15–0.7 eV. The segregation energy for ideal boundary is less than that for a boundary with defects.