共查询到11条相似文献,搜索用时 147 毫秒
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To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V. 相似文献
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用于电源线间ESD保护的新型高维持电压的SCR-LDMOS器件 总被引:1,自引:1,他引:0
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD(electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs. 相似文献
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As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements. 相似文献
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静电在我们周围随处可以产生,虽然对人体影响不大,但对一些电子元器件却能产生很大影响。有多种办法可以减少甚至消除静电的影响。文中从人体、机器、材料、环境、方法五个方面来介绍了静电的防护。 相似文献
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The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance. 相似文献
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The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators. The total heat and lattice temperature distributions along the Si-SiO_2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail. The influence of structure parameters on peak lattice temperature is also discussed, which is useful for designers to optimize the parameters of LDMSO for better ESD performance. 相似文献
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静电放电(ESD)对半导体器件,尤其是金属氧化物半导体(MOS)器件的影响日趋凸显,而相关的研究也是备受关注.综述了静电放电机理和3种常用的放电模型,遭受ESD应力后的MOS器件失效机理,MOS器件的两种失效模式;总结了ESD潜在性失效灵敏表征参量及检测方法;并提出了相应的静电防护措施. 相似文献