基于LC阻抗网络降低芯片信号反射的方法研究

为了降低电路在更高速率工作时的信号反射,任意给定0～100 GHz范围内的频率点,引入LC阻抗网络,分析其适用范围并求解各给定频率点对应的LC网络,最后,在常规互连线模型的终端门电容处就近接入LC网络,使得互连线的输入阻抗与其特性阻抗相当,从而保证了信号传输路径的阻抗连续性。与阻抗匹配前比较,各给定频率点及其附近一定带宽的反射系数都有效降低,从而验证了LC网络对降低高频信号反射的正确性。基于LC网络的匹配方法同样适用于多处阻抗不连续的多层芯片结构。     

高速电路设计中信号完整性的反射分析

针对高速电路设计中信号完整性的问题,文中通过对高速电路中传输线等效电路的分析,从理论及计算角度给出了信号反射现象的形成原因。介绍了两类常用的抑制反射的端接方案, 阐述了6种阻抗端接匹配方法消除反射的原理。通过Cadence公司的SpecctraQuest仿真工具对点对点信号传输网络进行了反射仿真,给出了在不同阻抗匹配方式下的仿真测试结果。结果表明,适当的阻抗匹配方式可以改善信号传输的反射现象。     

THru—Si公司推出一种制造多层堆垒芯片三维封装的新技术

Thru-Si Technologies公司(位于美国加州的Sunnyvale)开发了一种新技术,可以将多个含有不同功能线路的(例如存储器,逻辑线路,模拟线路和数字线路等)芯片堆垒在一起进行封装。此项技术,称为S-WLP(stacked wafer-level package,堆     

一种云服务器互连芯片交叉开关的设计与实现

在高端云服务器系统中,计算节点间的互连芯片通过Cache一致性协议将多计算节点互连组成分布式和共享内存空间系统,对接口传输速率和路由交换效率要求较高。文中通过分析Cache一致性协议报文的传输特点和互连网络转发需求,设计实现了一种互连芯片的高阶非对称交叉开关。设计通过了系统级的仿真验证,基于FPGA实现的云服务器互连芯片原型验证系统进行了实际带宽测试和芯片带宽匹配优化。互连芯片流片后的系统实测结果表明,满足功能要求,互连网络处理模块延迟8. 75ns,吞吐率65. 03%,达到了设计目标。     

芯片倒装封装中焊球及铜互连对高速差分信号传输特性影响的仿真研究

焊球与铜互连是芯片倒装封装中两种主要的互连结构,而随着数字电路时钟频率的不断提升,差分信号已成为高速数字电路中最常用的信号形式。采用HFSS全波仿真方法对芯片倒装封装中高速差分信号在差分对焊球和铜互连结构中的传输特性进行了研究。首先在理想情况下对差分对焊球结构进行了建模,分析了焊球阵列中焊球的尺寸和节距参数对差分信号传输特性的影响,发现在假定焊球节距为焊球直径2倍的情况下,现阶段常用的直径为0.1~1.27 mm的焊球中焊球尺寸和节距越小越能在宽频段内实现更好的传输性能。其次对平行式和内弯式、外弯式非平行差分铜互连结构进行了对比研究,发现平行式结构优于内弯式非平行结构,内弯式非平行结构优于外弯式非平行结构。     

一种非均匀采样重构芯片热信号的方法

实时片上热信号是集成电路芯片动态热管理(DTM)的重要信息。提出了一种基于Voronoi图的非均匀采样重构芯片热信号的方法,该方法在16核的处理器上每核9个传感器的情况下给出了最小2.25%的平均误差,并且通过与距离倒数加权平均法的平均运行时间的对比验证了该种方法的优越性。     

一种数字调频系统专用频率合成芯片的设计

针对汽车音响收音数字调谐系统实例,介绍了一种广播用双波段锁相环频率合成芯片的设计方法.本设计采用串行端口按位传输数据的方式,在程序分频器部分使用了吞脉冲技术,不仅简化了控制器的操作,同时也获得了较高的频率分辨力.     

一种与VLSI技术兼容的新型三维集成射频干扰滤波器

基于双π型电磁干扰滤波器(EMIF)的电路结构，借鉴集成电路超微细加工技术，提出了与等平面超大规模集成电路工艺完全兼容的一种新型三维集成射频干扰滤波器电路；简要介绍了该电路的绝缘层上金属薄膜三维集成制造方法，建立了电路传递函数模型，并进行了简要分析。该电路可用于制作适合未来电子系统高频化、小型化、轻型化和片式化信号处理的RF片上系统。     

一种新型的全局互连结构及其加工方法

随着特征尺寸的缩小,互连成为制约集成电路性能提高和成本下降的主要因素.为了降低互连延迟,提出了一种全新的全局互连结构,即利用掩膜电镀和CMP技术形成三维的铜互连结构,再利用牺牲层技术将三维结构镂空,得到悬空的全局互连结构.该结构可大大地降低全局互连对延迟的影响.     

2TF:一种协同考虑过硅通孔和热量的三维芯片布图规划算法

 三维芯片由多个平面器件层垂直堆叠而成,并通过过硅通孔(TSV,Through Silicon Via)进行层间互连,显著缩短了互连线长度、提高了芯片集成度.但三维芯片也带来了一系列问题,其中单个过硅通孔在目前的工艺尺寸下占据相对较大的芯片面积,且其相对滞后的对准技术亦降低了芯片良率,因此在三维芯片中引入过多的过硅通孔将增加芯片的制造和测试成本.垂直堆叠在使得芯片集成度急剧提高的同时也使得芯片的功耗密度在相同的面积上成倍增长,由此导致芯片发热量成倍增长.针对上述问题,本文提出了一种协同考虑过硅通孔和热量的三维芯片布图规划算法2TF,协同考虑了器件功耗、互连线功耗和过硅通孔数目.在MCNC标准电路上的实验结果表明,本文算法过硅通孔数目和芯片的峰值温度都有较大的降低.     

基于信号返回路径宽度的阻抗匹配技术研究

在高速电路设计中,信号源、传输线、负载之间的阻抗是否匹配是决定电路系统中信号完整性优劣的关键因素。针对该问题,从微带线的信号返回路径宽度与传输线特性阻抗之间的关系出发,经研究分析发现:通过改变微带线的信号返回路径宽度,可以有效控制传输线的特性阻抗,从而实现信号源、传输线、负载之间的阻抗匹配,使系统获得较好的信号完整性。同时给出经验公式。并通过实验仿真,其结果表明提出的方法是解决电路系统中阻抗匹配问题的有效途径之一。     

2.5D转接板封装高频互连结构设计、分析与测试

An interposer test vehicle with TSVs(through-silicon vias) and two redistribute layers(RDLs) on the top side for 2.5D integration was fabricated and high-frequency interconnections were designed in the form of coplanar waveguide(CPW) and micro strip line(MSL) structures. The signal transmission structures were modeled and simulated in a 3D EM tool to estimate the S-parameters. The measurements were carried out using the vector network analyzer(VNA). The simulated results of the transmission lines on the surface of the interposer without TSVs showed good agreement with the simulated results, while the transmission structures with TSVs showed significant offset between simulation and test results. The parameters of the transmission structures were changed,and the results were also presented and discussed in this paper.     

A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.     

三维集成电路中TSV-TSV的耦合分析与优化

TSV-TSV耦合会对三维集成电路的性能造成影响,主要的负面效应就是引入了耦合噪声。为了能够在初期设计阶段准确的估计TSV间的耦合强度,本文首先提出了存在于TSV间的基于二端口网络的阻抗级耦合通道模型,然后推导出了TSV间的耦合强度公式用来描述TSV-TSV耦合效应。通过与三维全波仿真结果的对比,公式的准确度得到了验证。另外,本文提出了一种减小TSV间耦合强度的设计方法。通过SPICE仿真,所提出设计方法不仅可以应用在简单TSV-TSV的电路结构中,还可以应用在含有多个TSV的复杂电路结构中,从而体现了所提出设计方法的可行性,并且为设计者提供了改善三维集成电路电学性能的可能性。     

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.     

嵌入式ARM系统PCB设计中信号完整性的研究

嵌入式高速系统PCB设计中信号完整性问题,是确保嵌入式系统安全可靠性的基础。本文针对嵌入式ARM系统PCB设计中,因电路布局和传输线阻抗失配造成信号反射而引起信号完整性的问题,通过对传输线效应和阻抗失配的理论分析,借助于Multisim2001仿真分析软件中的SPICE模型进行仿真研究。研究结果表明,阻抗匹配设计是解决传输线效应之信号完整性问题的关键,传输线模型的仿真结果与理论分析相符,基此,提出了避免传输线阻抗的不连续性和不要使用分支线的原理及方法,以期对嵌入式系统PCB设计具有一定的参考价值。     

光模块中刚柔线路板电连接宽带阻抗匹配研究

文章分别对光收发组件中50 Ω柔性线路板和50 Ω刚性线路板,以及25Ω柔性线路板和50Ω刚性线路板间的电互连阻抗匹配进行了设计、仿真与实验验证.对于50 Ω_50 Ω刚柔板的高频连接,通过对其返回路径的通孔位置优化设计,使反射损耗Su在高频段降低约11％,插入损耗S21减小190％;对于25 Ω_50 Ω刚柔板的高频连接,提出新的优化方式:在硬板信号线的金手指上做通孔设计,并提取该结构的寄生参数,构建电路模型.该结构大幅提高了连接处容性阻抗,降低了阻抗失配,使得S11在高频段降低约38.2％,S21减小约34％.提出的柔性线路板与刚性线路板的电互连方式,能实现传输线间的阻抗匹配,减小信号反射和插入损耗,提高光模块传输质量,对于光器件的接入具有较大应用价值.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.     

S-parameters-based high speed signal characterization of Al interconnect on low-k hydrogen silsesquioxane-Si substrate

The International Technology Roadmap for Semiconductors (ITRS) predicts that by 2010 over one billion transistors will be integrated into one chip [Semiconductor Industry Associations, International Technology Roadmap for Semiconductors, 2004. Available from: <http://public.itrs.net/Files/2004UpdateFinal/2004Update.htm>]. The interconnect system of this one billion transistor chip will provide the required high-speed signal and power to transmit each transistor on the chip. This system will deliver high frequency signals to various circuits, and the parasitic effects associated with interconnect will become evident and cannot be ignored. Small parasitic capacitance (C) between interconnect are required to reduce the crosstalk, power consumption, and RC delay associated with the metal interconnect system. Therefore, interconnect with low dielectric constant (k) materials is required.In this study, hydrogen silsesquioxane (HSQ) thin films prepared under various conditions are employed as the intermetal dielectric and the high frequency characteristics of Al-HSQ system are investigated and compared with those of Al-SiO₂ system. The S-parameters of the Al interconnect are measured for insertion loss and crosstalk noise. The interconnect transmission parameters are extracted from the S-parameters. A figure of merit (FOM) is employed to evaluate the characteristics of the Al-HSQ system at high frequencies (100 MHz-20 GHz). It is found that Al interconnect with HSQ films annealed at 400 °C has an insertion loss of 1.64 dB/mm, a coupling of −13.3 2 dB at 20 GHz, and a propagation delay of 0.121 ps/μm, while those of the PECVD SiO₂ films are 2.01 dB/mm (insertion loss), −13.40 dB (coupling), and 0.149 ps/μm (propagation delay). The Al-400 °C-annealed-HSQ system has better performance than the Al-SiO₂ system does from 100 MHz to 20 GHz. However, specimens with 350 °C-annealed HSQ films or plasma-treated HSQ films exhibit larger insertion losses and higher crosstalk noises than those with PECVD SiO₂ films do. Both annealing temperature and O₂ plasma treatment of the HSQ films affect the high frequency characteristics of the Al-HSQ system.