RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor

The development of a real-time infrared search and track (IRST) processing system served as a real-world test of progress toward the fourfold reduction in cycle time expected at the end of the four-year Rapid Prototyping of Application Specific Signal Processors (RASSP) program. This signal processor development tested the effectiveness of the RASSP methodology and processes and provided critical metrics to evaluate the 4X roadmap. Virtual Prototyping, a VHDL technique for validating hardware and software design before building hardware, makes the RASSP top-down methodology unique. This paper describes the 4X roadmap for cycle time improvement, our experiences with virtual prototyping and important lessons learned for improving the methodology.     

Rapid Prototyping of Application-Specific Signal Processors (RASSP) In-Progress Report

The goal of the DARPA/Tri-Service-sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to reduce the cost and time to develop and manufacture signal processors by at least a factor of four. Lockheed Martin Advanced Technology Laboratories' (ATL) approach to reaching this goal is based on three thrusts: methodology, model-year architecture, and infrastructure (enterprise). The Advanced Technology Laboratories' RASSP team—composed of an alliance of companies—implemented the first baseline RASSP system, which advances today's state-of-the-art by a factor of >2X. The Advanced Technology Laboratories' RASSP team used the methodology and tools to demonstrate cost and design-cycle improvements on the benchmark virtual proto-type, and developed a hardware/software system that demonstrated first-pass success. Additional developments underway will provide further benefits and will demonstrate 4X improvements in cost and time to market. This paper updates the team's progress halfway through the program, and highlights the impact of using the RASSP concepts on the design of a SAR processor, a Navy standard processor upgrade, and a CNI application.     

高分辨率SAR实时信号处理

介绍了高分辨率合成孔径雷达实时信号处理机硬件结构和实时信号处理算法及流程。该信号处理机的核心是G4模块，包含4个矢量处理芯片MPC7410，G4模块具有存储容量大和运算速度快的特点。算法上采用工程上较易实现的R-D算法及对比度最优自聚焦算法。利用机载SAR试飞数据验证，得到了高分辨率SAR图像，证明信号处理机稳定有效可靠。     

高性能通用信号处理器

高度集成了8片ADSP-TS201的高性能信号通用处理器,主要用于完成标准CPCI总线平台下雷达信号处理任务,具备高速数据传输,海量数据处理,和主机交互等性能,其超强的实时性、处理能力和兼容性能很好的满足现在各种新体制雷达信号处理系统的要求。     

基于PC机的信号处理机

介绍一种基于PC机的信号处理机，并给出硬件框图和软件流程图。     

浅谈数字信号处理器

本文对数字信号处理器进行了概括和分析，涉及了数字信号处理器的发展，并结合其软硬件特点，讨论了数字信号处理器的优势，提出了数字信号处理器现阶段所面临的问题和挑战。     

Sequential Multistate EMG Signal Processor

A feature of multifunction EMG control is that the operator is always aware when a decision is made. Thus, a sequential processor which observes the EMG signal for the length of time necessary to make a reliable decision would be a logical one. In this paper, two sequential processors are developed for the EMG signal. Exact expressions for the processor performance, error probability, and the average number of samples required to make a decision are derived. The two processors are modeled on a computer and verified experimentally. Both the theoretical and experimental results show that compared to an optimal Bayes receiver the sequential processor, for a given efror probability, requires, on the average, approximately half the number of samples. Finally, a proof is given for the optimum signal set and this set is used in the paper.     

模块化信号处理机技术探讨

叙述模块化信号处理机的基本组成和工作原理 ,对信号处理过程中部分关键技术和发展趋势进行探讨     

无人机载SAR实时信号处理系统设计

针对合成孔径雷达实时成像处理中数据量大、数据吞吐率高、成像算法实现复杂等特点,设计了适合于无人机载SAR实时信号处理系统的硬件平台和实时信号处理算法流程。该信号处理系统包括一块带有AD采集功能的接口板和两块以TS201为核心处理器的信号处理板。考虑到实时性要求和无人机平台的不稳定性,设计了一种结合惯导和回波数据进行运动补偿的改进型RD成像算法。在无人机平台上成功稳定地实现大面积连续实时成像,证明信号处理系统稳定可靠,实时信号处理算法可行。     

宽带信号处理器BSP-15

随着多媒体技术的广泛应用，采用DSP芯片设计多媒体设备，成为人们关注的方向，但是，对于可编程的媒体处理器的需求也很高。因此，一种新型的DSP芯片——媒体处理器(Media Processor)应运而生，并很快得到业界的广泛关注，而本文介绍的BSP-15正是一款典型的媒体处理器。BSP-15是专门以视频应用为中心而设计的高效DSP，以高度集成的单芯片满足了宽带产品的需要。本文介绍了BSP-15的性能、结构及其软件开发，并给出了基于BSP—15的软件并行设计。     

某雷达信号处理机调试台的设计

在雷达系统中,信号处理机是核心部件之一,其性能参数及可靠性直接影响到雷达系统的性能。怎样全面系统测试信号处理机,是我们关心的问题。本文介绍了一种有效的信号处理机测试平台的设计。     

A Simple Signal Processor for a Respiratory Rate Monitor

Although respiratory rate is a desirable patient parameter to monitor, signals from a spontaneously breathing patient are so irregular that reliable counts have been difficult. This short communication describes a circuit that processes the signal produced by a respiratory transducer (in our case an impedance pneumograph), and provides a countable output to a digital rate monitor. It is relatively simple, but embodies complex decision criteria in identifying respiratory activity.     

一种实用的红外弱小目标检测跟踪处理机研究

以小波变换作为对红外弱小目标进行检测识别的核心算法，并根据该算法搭建了基于FPGA和DSP的红外信号处理器的硬件平台。该平台在FPGA上实时完成了离散小波变换算法，可用于检测弱小目标，并通过DSP实现了稳定地跟踪。结果表明，该设计的方案对红外弱小目标的检测识别和跟踪具有实际意义。     

带噪声抑制的音频信号处理器

文中介绍一种可以实现电子音量噪声抑制的模块。该模块主要有运算放大器模块、可调电阻Rf模块、I2C总线控制模块、数据缓冲模块、增益数据模块、时间基准模块、分压模块和输出缓冲模块组成。文章介绍了音频信号处理芯片的组成及原理,重点对音量控制部分进行阐述,对数字音量控制开关产生的噪声抑制方法进行了详细的分析。该芯片采用BICMOS工艺,工作电压在9V左右,实现了低失真低噪声的音频信号处理。     

A High Performance LSI Digital Signal Processor for Communication

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.     

面向雷达信号处理应用的可重构处理器设计

为满足现代雷达的高性能应用需求,文中提出并设计了一种可重构专用处理(RASP)架构。其采用非规则化微结构和混合重构策略,有效提升了并行流水计算的性能;通过兵乓处理机制掩盖DDR读写时间,充分发挥了运算资源的效率。RASP作为硬件加速核嵌入华睿2号DSP芯片并于TSMC 40 nm工艺下完成流片。测试结果显示,RASP完成1 K(1 024)点FFT的运算时间为2.57μs,处理效率高达42%,相比于NoC、MorphoSys、C6678、T4240等处理器,性能提升至1. 9~30倍,效率达到1.25~4 倍。     

国产高性能通用数字信号处理器的DEMO板设计

为了向用户演示高性能芯片BWDSP100,设计了一款DEMO板。通过该板可以向用户演示芯片的功能、性能等。板卡采用经典FPGA+DSP结构,处理功能强大,控制灵活。在设计过程中,贯彻以用户为中心的设计思想,不仅做到让用户使用方便,还要全面演示芯片。     

数字信号处理器分布式寄存器的写回设计

针对分布式寄存器文件应用于高性能超长指令字（VLIW）数字信号处理器而造成的分支流水线与写回控制信号的同步问题,提出了一种面向分布式本地寄存器文件的写回策略。其中包括指令执行周期的产生,写回信号缓存以及写回控制单元。采用了面积功耗性能评估方法,结果证明了该策略能充分发挥分布式寄存器文件在功耗方面的优势,相对于运用集中式寄存器文件可以减少50％的功耗,同时对于传统流水线写回控制方法可以节省60％的面积开销。     

VTS雷达信号处理器的设计与实现

主要研究VTS（船舶交通管理）系统中的雷达信号处理系统。该系统采用基于DSP＋CPLD机制的实时信号处理板，两片C6X系列的高性能DSP和一大片大规模逻辑器件，实现对原始的雷达视频信号的各种处理：电子地图屏蔽、双极点滤波、匹配滤波、STC（Sensitivity Time Control)、恒虚警以及雨杂波处理。充分发挥DSP处理的优越性，在各种噪声和杂波中快速而准确地提取出船舶的各种信息，实现港口船舶的实时探测、定位和显示，并生成各种信息的统计报告。该处理器实际使用效果良好。