跨阻放大器的带宽扩展技术

提出了一种针对CMOS跨阻放大器的带宽扩展技术.基于此技术,采用应用于0.18μm 1.8V CMOS工艺,设计了一个RGC结构的跨阻放大器.仿真结果表明,该放大器具有66dB的跨阻增益,4.49GHz的带宽,输入等效噪声电流平均值为11.5pA/(Hz)～(1/2),该电路的功耗仅为15.4mW.     

基于SiGe BiCMOS工艺的25Gbit/s跨阻放大器设计

采用0.25 μm SiGe双极CMOS (BiCMOS)工艺设计并实现了一种传输速率为25 Gbit/s的高速跨阻前置放大器(TIA).在寄生电容为65fF的情况下,电路分为主放大器模块、两级差分模块和输出缓冲模块.相比传统的跨阻放大器,TIA采用Dummy形式实现了一种伪差分的输入,减小了共模噪声,提高了电路的稳定性;在差分级加入了电容简并技术,有效地提高了跨阻放大器的带宽;在各级之间引入了射极跟随器,减小了前后级之间的影响,改善了电路的频域特性.电路整体采用了差分结构,抑制了电源噪声和衬底噪声.仿真结果表明跨阻放大器的增益为63.6 dBQ,带宽可达20.4 GHz,灵敏度为-18.2 dBm,最大输出电压为260 mV,功耗为82 mW.     

56 Gbit/s PAM4 CMOS光接收机前端电路设计

基于65 nm CMOS工艺设计了一种56 Gbit/s PAM4光接收机前端放大电路.前级为差分形式的跨阻放大器,采用共栅前馈型结构降低输入阻抗,并在输入端串联电感,有效提高了跨阻放大器的带宽和灵敏度.后级放大器采用具有线性增益控制的多级级联可变增益放大器,实现对输出摆幅的自动控制.输出缓冲器采用源极退化技术来拓展带...     

40-Gbit/s SDH光纤通信系统前置放大器设计

基于0.35μm SiGe BiCMOS工艺,设计了共基极和共发共基两种输入结构的前置放大器.为获得更宽的电路带宽,共基极电路采用了电容峰化技术.电路仿真表明,采用这些技术使两种前置放大器的跨阻带宽都达到了28GHz以上,满足了40Gbit/s SDH光纤通信系统带宽要求.通过比较两种不同输入结构前置放大器的增益、带宽、电路稳定性以及噪声特性,提出了双极型晶体管实现高速前置放大器的设计方案.     

一种基于40 nm CMOS工艺的40 Gbit/s低噪声跨阻放大器

采用40 nm CMOS工艺,设计了一个工作在40 Gbit/s数据速率的高速低噪声跨阻放大器(TIA)。为了同时兼顾噪声和带宽性能,创造性提出了一种多级串联跨阻放大器结构。输入级采用基于反相器结构的伪差分跨阻放大器,通过增加反馈电阻来减小输入电流噪声,第二级的前向运放用来抑制后级均衡器的噪声,第三级用连续时间线性均衡器(CTLE)对前级不足的带宽进行补偿,后面的三级限幅放大器(LA)对电压信号进一步放大。限幅放大器利用并联电感峰化技术和负跨导技术来提高带宽和增益。最终,信号由输出驱动器(OD)输出到片外,输出驱动器采用T-COIL技术。仿真结果表明,整条链路可以实现84 dBΩ和63 dBΩ的跨阻增益,带宽分别为31 GHz和34 GHz,输入电流积分噪声(rms)为1.75 μA。     

10 Gbit/s GaAs 跨阻前置放大器

GaAs基pHEMT工艺适合于制作10Gbit／s速率的高速前置放大器电路。完成了工作于10Gbit／s速率的跨阻前置放大器电路的器件设计、电路设计,电路采用了串联电感L技术,有效地提高了工作带宽。模拟工作带宽达到9．0GHz,跨阻增益达到58dBt2。电路采用0．2pmGaAs基pHEMT电子束直写T型栅工艺制作。对制作的电路进行了电测试,可工作于10Gbit／s的速率。     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

一种宽输入动态范围跨阻放大器的设计

利用对数放大的增益可变性特点,设计出基于对数放大的跨阻放大器,克服了采用传统AGC调整跨阻的复杂性和低可靠性;同时,避免了采用肖特基二极管箝位方法的工艺局限性,有效扩展了跨阻放大器的输入动态范围。在详细分析跨阻动态特性及温度特性的基础上,分析了电路噪声性能,并进行了仿真验证。试验样片的测试结果进一步证明所提出的方法是有效的。     

基于InGaAs/InP SHBT技术的10 Gb/s单片跨阻放大器研究

介绍了采用传统的三台面工艺,利用湿法选择腐蚀形成发射极.基极自对准的InGaAs/InP单异质结双极性晶体管(SHBT)技术实现传输速率为10 Gb/s跨阻放大器.其中SHBT获得了在Ic=10 mA,Vce=2 V时,fT和fmax分别为60、75 GHz,电流密度为100 kA/cm2,击穿电压大于3 V;跨阻放大器的跨阻增益为58 dBΩ,灵敏度为-23 dBm,3 dB带宽为8.2 GHz.该单片跨阻放大器可广泛应用于光纤通信.     

6 GHz transimpedance amplifier for optical sensing system in low-cost 0.35 /spl mu/m CMOS

A high-speed transimpedance amplifier (TIA) has been designed and implemented in a low cost 0.35 mum CMOS technology. Combining the techniques of regulated cascode input stage, current shunt feedback and inductive-series peaking, the TIA achieves a transimpedance gain of 51 dBOmega and 3 dB bandwidth of 6 GHz, in the presence of a photodiode capacitance of 0.6 pF. This is believed to be the fastest TIA ever reported in 0.35 mum CMOS technology     

SiGe differential transimpedance amplifier with 50-GHz bandwidth

InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-/spl Omega/ transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA//spl radic/Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dB-/spl Omega/ transimpedance and 49-GHz bandwidth.     

A CMOS Tunable Transimpedance Amplifier

A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-mum CMOS process. Consuming a dc power of 34mW from a 2.0-V supply voltage, the fabricated TIA exhibits a variable -3-dB bandwidth from 3.9 to 7.6GHz while maintaining a transimpedance gain of 52dBOmega. With a 7.5-Gb/s 2³¹-1 pseudo-random bit sequence, the measured input sensitivity of the TIA is -19 dBm at a BER of 10^-12     

The tradeoff between noise,data rate,and power consumption of transimpedance amplifiers for optical receivers

Analog Integrated Circuits and Signal Processing - The inverter-based shunt-feedback transimpedance amplifier (TIA) has become an essential building block for high-speed receivers for optical...     

High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector

We present a high-speed monolithically integrated optical receiver fabricated with 0.13-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10^-12 at the incident optical power of - 5.5 dBm.     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

A 49-GHz preamplifier with a transimpedance gain of 52 dBΩusing InP HEMTs

This paper describes a new preamplifier IC with 0,15-μm gate InP-based high electron mobility transistors (HEMTs) for a high-speed fiber optic communication system. The preamplifier consists of a lumped-element transimpedance amplifier (TIA) for the input stage and a highly stabilized distributed amplifier with cascode-configured unit cells for the gain stage. A gain-peaking technique for a distributed amplifier was employed to enhance the bandwidth and gain flatness of the preamplifier. This gain peaking profile compensates for a lack of bandwidth of a TIA. As a result, we achieved a flat transimpedance gain of 52 dBΩ and a bandwidth of 49 GHz     

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

Current-mode analogue interface for high-speed low-current differential signalling

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpedance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 Ω differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8 V, 0.18 μm digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57 μA and 5.75 GHz, respectively. For the targeted BER of 10^?12, a data transfer rate of 6 Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20 cm. The power dissipated in the current-mode receiver is 3.6 mW.