Achievements in rotary head magnetic recording

The principal achievements since 1980 in rotary head recording on magnetic tape are outlined. These developments are related to fundamental improvements in recording media, heads, the design of tape transports, and signal processing. The D-1 and D-2 video tape recorders (VTRs), the Hi-Band 8-mm video cassette recorder (VCR), and the rotary digital audio tape (R-DAT) recorders are discussed. The future of rotary head recorders for consumer digital VCRs, professional high-definition TV (HDTV) VTRs, and consumer HDTV VCRs is assessed     

Trends in digital magnetic recording; the application of thin-film heads for tape recording

Digital tape recording systems show the same trend as hard-disk drives: a large increase of storage density with time. The use of advanced media and highly sensitive thin-film heads with magnetoresistive (MR) readout will increase the storage density dramatically. Key improvements are narrower tracks, more sensitive MR elements attained by applying the giant magnetoresistance effect, high-saturation flux density pole materials, advanced metal powder tape, intimate head-to-tape contact, and accurate tracking. By increasing the number of channels in the multitrack thin-film head, high data rates can be obtained as well. The basics of digital magnetic recording are discussed and a short historical overview is given of the Philips activities on thin-film heads for tape recording. An outlook on future improvements is given.     

High-density magnetic recording heads

This paper outlines the important dimensions and parameters of high-density heads and discusses why each is important and how they are related. Among factors discussed are: head-to-media spacing, record gap size, media coercivity and remanence, record demagnetization fields, record gap-edge saturation in ferrite, metal, metal-in-gap, and thin-film heads, and head wear. Gap-edge straightness is discussed. Magnetoresistive read heads are described. Vertical recording and pole-type heads are discussed. Principle sources of head noise are outlined.     

超高频射频识别读写器的研究与设计

超高频射频识别系统具有存储容量大、读写速度快、识别距离远和可同时读写多个电子标签等特点,已经在众多领域得到了广泛的应用。为了满足市场需求,对超高频读写器的内部结构进行了研究并提出了一种基于ARM的超高频射频识别系统读写器的设计方案。从硬件和软件两个方面对读写器的设计进行了阐述,给出了读写器的设计结构、工作流程以及相关的软件流程图。实际应用结果表明,该读写器具有读写速度快、读写效率高、识别距离远等优点,可以满足市场需求。     

Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability

In this work, we proposed a single-ended read disturb-free 9T SRAM cell for bit-interleaving application. A column-aware feedback-cutoff write scheme is employed in the cell to achieve higher write margin and non-intrusive bit-interleaving configuration. And a dynamic read-decoupled assist scheme is utilized by cutting loop to relax the interdependence between stability and read current, resulting in robust read operation and better read performance simultaneously. Moreover, the lower write and leakage energy consumptions are also achieved. We compared area, stability, SNM sensitivity and energy consumption between proposed 9T and standard 6T bit-cells. The write ability of 9T cell is 1.40× higher that of 6T cell at 1.0 V, and 8.16× higher at 0.3 V. The write and leakage energy dissipations are 26% and 13% lower than that of 6T at 1.0 V. In addition, robust read and better process variation tolerance are provided for proposed design with area penalty.     

基于VHDL的异步FIFO设计

FIFO经常应用于从一个时钟域传输数据到另一个异步时钟域。为解决异步FIFO设计过程中空满标志判断难以及FPGA亚稳态的问题,提出一种新颖的设计方案,即利用格雷码计数器（每次时钟到来仅有1位发生改变）表示读／写指针,设计二级同步链为跨越不同时钟域的读／写指针,以提供充足的稳定时间,并通过对比格雷码指针产生空满标志位。该设计采用VHDL语言进行设计,利用ALTERA公司的FPGA得以实现。经验证进一步表明,模块化的设计不仅避免了亚稳态的产生,增大平均无故障工作时间（MBTF）,也使工作效率大为提升。     

基于DMA的大批量数据快速传输模块设计

针对Altera公司SOPC解决方案中,DMA模块无法直接读/写FPGA外设的情况,提出了基于Avalon总线流传输模式的通用DMA读/写控制模块的设计,设计了两个自定义外设,实现了DMA对FPGA外设的高速数据存取和Nios II与FPGA大批量数据的快速传输。介绍了Avalon-MM总线规范,阐述了系统架构以及DMA读控制器的设计,测试结果表明,该方法是一种高效可行的解决方案。     

忆阻器的建模及高精度忆阻值读写电路的设计

使用现有电路元件设计了一种荷控忆阻器的理论模型。由于把忆阻器应用于存储器、神经网络、信号处理等领域均涉及到忆阻器的读写操作,并且目前忆阻器大多是数字量0和1的操作,没有模拟量的操作。所以利用了荷控忆阻器的电荷特性,给出一种描述如何读取忆阻器的模拟忆阻值的方法。利用了荷控忆阻器的频率特性,设计了一个反馈式忆阻值写电路,该电路能够在忆阻器的阻态范围内进行任意模拟量的写操作。仿真结果验证了设计的正确性。     

压电微执行器在硬盘伺服系统的应用研究

介绍一个硬盘双伺服控制系统的设计和实现。双伺服系统是在硬盘固有的音圈电机上附加了一个压电微执行器,用来执行更快捷、精确的磁头定位。对音圈电机的控制设计采用了一种线性反馈控制技术,结合扰动估计和补偿实现快速、平稳和无静差的设定点跟踪。基于开环逆控制的思想,微执行器环路的控制采用定值比例及滤波器,使得合并的位移输出能更快地跟踪设定点(磁道)。仿真和实验结果证明双伺服控制系统可以实现更快速、精确的磁头定位。     

超高频射频识别读写器的研究与设计

超高频射频识别系统具有存储容量大、读写速度快、识别距离远和可同时读写多个电子标签等特点,已经在众多领域得到了广泛的应用。为了满足市场需求,文章对超高频读写器的内部结构进行了研究,并提出了一种基于ARM的超高频射频识别系统读写器的设计方案。文中从硬件和软件两个方面对读写器的设计进行了阐述,给出了读写器的设计结构、工作流程...     

Design of a single-ended energy efficient data-dependent-write-assist dynamic (DDWAD) SRAM cell for improved stability and reliability

A data-dependent write-assist dynamic (DDWAD) SRAM cell is proposed to reduce the power consumption and enhance the relaibility against process, voltage, temperature variation and aging effect under static stress. The cell has distinct read and write circuits with single bit line for respective operations which improve the read stability. In the cell, write operation is performed using separate write signal WS instead of wordline WL. The write signal WS is introduced to reduce the discharging actvity at the write bit line BL to reduce the dynamic power consumption. The latch property of the cell is disabled during write operation to flip the data faster at the storage nodes. The proposed design approach provides high immunity to the data-dependent bit line leakage and results in lower voltage drop on BL, lower leakage current and lower parasitic capacitance. The proposed cell consumes approximately 60.4 % lower write power and 52.8 % read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell can be maintained even if the power supply is reduced to 300 mV.     

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture

In order to reduce static energy consumption, emerging Non-Volatile Memory (NVM) technologies such as Spin Transfer Torque Magnetic RAM (STT-MRAM), Spin-Hall Effect Magnetic RAM (SHE-MRAM), Phase Change Memory (PCM), and Resistive RAM (RRAM) are under intense research. Additionally, there is a demand for more reliable circuits as the technology scales due to increased error rates caused by the increased impact of Process Variation (PV). In order to combat PV-induced reliability problems, a novel approach is proposed herein that improves the reliability of read and write operations in emerging NVMs. In the proposed design, which is called the Self-Organized Sub-bank (SOS) approach, two Sense Amplifiers (SAs) have been adopted, one with improved reliability and one with improved energy efficiency profiles, in order to increase the performance of the read operation. In particular, based on the result of a Power-On Self-Test (POST), which detects PV-impact on sub-banks, SOS chooses between a reliable and an energy-efficient SA and assigns a preferred SA to each sub-bank. Furthermore, in order to increase the performance of the write operation, SHE-MRAM is replaced with STT-MRAM to provide better write energy profile. Additionally, SOS design is once implemented with a reliable write scheme and once with an energy-efficient write scheme and results are compared and analyzed. Based on the preliminary observation in our case study, 21.5% of read operations are extremely vulnerable to PV impacts. Our results indicate that the proposed SOS approach reduces the vulnerability of the read operation by 40% on average, hence reducing the fault propagation. In particular, the SOS alleviates Vulnerable False Data Sensing (VFDS) by 82% on average, while enhancing True Data Sensing (TDS) from 72.5% to 95% across all workloads studied herein compared to LLC with conventional STT-MRAM. Additionally, SOS using the reliable write circuit provides 161% improved Energy Delay Product (EDP) on average compared to SOS with conventional STT-MRAM, while providing less than 8% write current variation. On the other hand, SOS using energy-efficient write circuit offers 39% improved EDP on average compared to the SOS using reliable write circuit and 62% EDP improvement over conventional STT-MRAM.     

铁电存储器在存储测试系统中的应用

为了实现环境试验的存储测试系统,采用了FRAM存储器M28W640结合SOC片上系统C8051F340的设计,通过分析其性能和接口电路,编写了相应的读写程序。由于这种并行非易失性存储测试技术方式具有高速读写、超低功耗、几乎无限次擦写,读写程序编写简便的优点,非常适合在此类存储测试系统中使用。     

Multihead detection for multitrack recording channels

We look at multiple-track detection for magnetic recording systems that use array heads to write and read over multiple tracks simultaneously. The recording channel is modeled as having intersymbol interference (ISI) in the axial direction, and intertrack interference (ITI) in the radial direction. Optimum multihead and single-head detectors are derived and analyzed in terms of error-probability performance for various levels of intertrack interference. Among other results, it is seen that for a range of ITI levels, codes designed to increase distance in single-head systems can provide the same coding gains for multihead systems     

A 32-word by 32-bit three-port bipolar register file implementedusing a SiGe HBT BiCMOS technology

Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply     

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings.     

基于Xilinx PCI Express Core的高速DMA读写设计

本设计在基于Xilinx Virtex-6 FPGA内嵌PCI Express Core的基础上,实现了由PCI Express板卡主动发起的DMA读写,可完成PC和PCI Express板卡之间数据的高速传输。该设计已经在Xilinx评估板ML605上完成调试验证,DMA写内存速度稳定可达1 520 MB/s,满足了高速存储系统的要求。     

基于SRAM高速灵敏放大器的分析与设计

在SOC系统级芯片中,存储器占有很重要的地位。随着电路频率的提高,存储器的读写操作速度也要求相应的加快。SRAM中的灵敏放大器通过检测位线上的微小变化并放大到较大的信号摆幅以减少延时,降低功耗。本文提出了一种两级串联结构的SRAM高性能灵敏放大器的设计方法,降低了对信号的反应时间,提高了抗干扰能力,适应高频电路的读写操作。     

A novel nonvolatile memory cell suitable for both flash andbyte-writable applications

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors     

磁盘访问时间的近似计算方法

传统的磁盘访问时间由磁头寻道、盘片旋转和磁头读写3部分累加得出,通过引入随机变量和访问概率等数学工具来计算磁盘访问时间,具有精确度更高、实用价值强等优点。