A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A 4 mW 3–5 GHz current reuse g<Subscript>m</Subscript>-boosted short channel common-gate CMOS UWB LNA

A novel architecture is presented to optimize the noise performance and the power consumption of the transconductance ‘g_m’ boosted common-gate (CG) ultrawideband (UWB) low-noise amplifier (LNA), operating in the 3–5 GHz range, by employing current reuse technique. This proposed CG LNA utilizes a common source (CS) amplifier as the g_m-boosting stage and the bias current is shared between the g_m-boosting stage and the CG amplifying stage. The LNA circuit also utilizes the short channel conductance g_ds in conjunction with an LC T-network to further reduce the noise figure (NF). The proposed LNA architecture has been fabricated using the 130 nm IBM CMOS process. The LNA achieved input return loss (S₁₁) of −8 to −10 dB, and, output return loss (S₂₂) of −12 to −14 dB, respectively. The LNA exhibits almost flat forward voltage gain (S₂₁) of 13 dB, and reverse isolation (S₁₂) of −62 to −49 dB, with a NF ranging between 3.8 and 4.6 dB. The measurements indicate an input-referred third order intercept point (IIP3) of −6.1 dBm and an input-referred 1-dB compression point (ICP_1dB) of −15.4 dBm. The complete chip draws 4 mW of DC power from a 1.2 V supply.     

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

In this work a 2.2 GHz quadrature receiver front-end suitable for low-power applications is presented. The low-noise amplifier, the mixer and the voltage-controlled oscillator are merged into a single stage, making the circuit capable of extreme current reuse while keeping it still functional at low supply voltage. A careful linear time-variant analysis is proven to be necessary to accurately predict the conversion gain and the bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, validates the theoretical analysis, showing 27 dB of downconversion gain over a 14 MHz base-band bandwidth; the noise figure is 13 dB with a flicker corner frequency of 200 kHz; the input-referred 1 dB compression point is −23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.     

A low voltage current mode CMOS integrated receiver front-end for GPS system

This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 μm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (G_m-LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed G_m-LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I–V, V–I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred third-order intercept point (IIP₃) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

Low-power current-reused RF front-end based on optimized transformers topology

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC current. Measurements of performance show a conversion gain of 28.5 dB, noise figure of 6.6 dB, 1 dB compression point of −32.8 dBm and IIP3 of −23.3 dBm at a 250 kHz intermediate frequency, while dissipating 1.45 mA from a 1.2 V supply.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

High IIP3 and Low-Noise CMOS Mixer Using Non-linear Feedback Technique

A third-order intermodulation cancelation technique using a non-linear feedback is proposed to design a low-power low-distortion mixer in a 65 nm standard CMOS technology. The IM3 cancelation is achieved by estimating distorting error at a non-linear feedback element and subtracting it from the input. The linearization technique is utilized in the input trans-conductance of the mixer. The circuit functionality is analyzed using Volterra series. The covering frequency range of the mixer is 800 MHz to 5 GHz. The technique increases the input-referred third-order intercept point (IIP3) and input 1 dB compression point to +16.4 dBm and −1.87 dBm, respectively. It obtains a gain of 9 dB and an input-referred noise of 1.84 nV/?{}/\sqrt{}Hz while consumes 8.75 mA from 1.2 V supply. The layout of the mixer occupies 0.315 mm × 0.296 mm of silicon area.     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

Body effect up- and down-conversion mixer circuits for low-voltage ultra-wideband operation

This article presents fully differential up- and down-conversion mixer circuits manufactured in a triple well 45 nm CMOS process for low-voltage Ultra-Wideband transmitter and receiver applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the down-conversion mixer uses the bulk for switching via threshold voltage modulation, the up-conversion mixer applies the baseband signal to the bulk, thereby implicitly incorporating the back-gate controlled current source of the MOS transistor. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The down-conversion mixer features an input-referred compression point of −13.2 dBm and a maximum conversion gain of 9.4 dB at 2.5 GHz with the 3-dB corner frequency being beyond 10 GHz. The implemented up-conversion mixer offers a maximum conversion gain of −8.8 dB at 5.8 GHz together with an output-referred compression point of −9.7 dBm. The operational bandwidth ranges from 4.5 to 6.7 GHz. Both circuits operate at a low supply voltage of 1.1 V.     

A 6.4 mW, 4.9 nV/√Hz, 24 dBm IIP3 VGA for a multi-standard (WLAN,UMTS, and Bluetooth) receiver

A low-power high-linearity variable-gain-amplifier (VGA) to be embedded in a multi-standard receiver (WLAN, UMTS and Bluetooth) is reported. The multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, noise level, and common mode input voltage) for the three telecom standards. The VGA is positioned just after the mixer, and, then, it operates on low- amplitude input signals. This results in stronger noise requirements than linearity ones. Thus a digitally controlled open-loop structure has been used. The prototype VGA is realized in a 0.13 μm CMOS technology and it features gain levels from −10 to 36 dB. For 0 dB DC-gain it exhibits a 25 dBm IIP3 and an input-referred noise voltage lower than 5 nV/√Hz. This gives a 85 dB-DR for the WLAN case. The VGA draws 6.4 mA from a single 2.5 V supply.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90^deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.