73GHz磷掺杂多晶硅发射极自对准SiGe基区双极晶体管

报道了一种用来制作自对准SiGe基区异质结双极晶体管降低热处理周期的磷发射极工艺。短的热处理周期导致极窄的基区宽度,并维持轻掺杂的隔离层不消失,这种隔离层是为了提高击穿特性而制作在发射极-基极和基极-集电极内的。已获得了35nm基区宽度的晶体管,其发射极-基极反向漏电小,峰值截止频率为73GHz,本征基区薄层电阻为16kΩ/□。用这些器件获得的最小NTL和ECL门延时分别为28和34ps。     

超高速VLSI中多晶硅发射极晶体管串联电阻的测量

本文对目前流行的测量晶体管串联电阻的常规方法进行了理论分析和实验验证，结果表明，用常规方法测量多晶硅发射极晶体管串联电阻的误差很大。     

多晶硅有晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能的进行比较。结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了ＥＢ击穿和ＣＢ击穿,电流增益依赖于淀积多晶硅前的表面处理条件。     

多晶硅发射极晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能进行了比较.结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了EB击穿和CB击穿.电流增益依赖于淀积多晶硅前的表面处理条件.     

双多晶自对准NPN管的总剂量辐射效应研究

对国产先进互补双极工艺制作的双多晶自对准(DPSA)结构的NPN管进行了高、低剂量率的⁶⁰Co-γ源辐射实验。在总剂量辐射前后以及室温退火后,分别采用移位测试方法,研究了基极电流、集电极电流、电流增益等参数的变化规律。结果表明,DPSA NPN管比传统NPN管的抗辐射能力更强,但其低剂量率辐射损伤增强效应(ELDRS)改善不明显。最后,初步探讨了DPSA NPN管的辐射损伤机制,讨论了DPSA NPN管的抗ELDRS效应的机制。     

超高频多晶硅发射极晶体管的研究

本文描述了一种实现亚１００ｎｍ基区宽度的晶体管结构。加工工艺类似ＢＳＡ（硼硅玻璃自对准）技术，可实现亚１００ｎｍ的基区结深，还可解决自对准器件在横向和纵向按比例缩小时所遇到的困难。与离子注入工艺相比，这种工艺可轻易地解决诸如高剂量离子注入所产生的下列问题：二次沟道效应对基区结深减小的限制及晶格损伤。晶体管采用了多晶硅发射极，ＲＴＡ（快速热退火）用于形成晶体管的单晶发射区，为提高多晶发射区的杂质浓度     

亚微米双层多晶硅自对准双极晶体管性能研究

本文采用亚微米工艺和自对准技术制作了发射区宽度分别为0.8μm和0.4μm的两种双层多晶硅自对准双极晶体管。其中采用的是深沟和LOCOS两种隔离联合的隔离方法;EB间自对准是通过均匀的高质量的SiNx侧墙实现的,EB结击穿电压高达4.5V;窄的发射区使得发射极多晶硅在发射区窗口严重堆积,引起了双极晶体管的电流增益增大,同时也降低了管子的速度。工艺和器件模拟显示,发射极多晶硅采用原位掺杂技术,双极晶体管的性能得到了很大的改善。     

Self-Aligned Top-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Self-aligned techniques are often used in conventional CMOS and Si-based thin-film transistors (TFTs) technologies due to various merits. In this paper, we report self-aligned coplanar top-gate InGaZnO TFTs using PECVD a-SiN$_{x}$:H patterned to have low hydrogen content in the channel region and high hydrogen content in the source/drain region. After annealing to induce hydrogen diffusion from a-SiN$_{x}$:H into the oxide semiconductor, the source–drain regions become more conductive and yet the channel region remains suitable for TFT operation, yielding a working self-aligned TFT structure. Such fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.      

Selective Polysilicon Oxidation Technology for VLSI Isolation

Field isolation technology is described for small geometry VLSI's in which selective polysilicon oxidation is essential. The technology, also known as SEPOX, offers resist pattern reproducibility in field oxide, while maintaining crystal perfection in the substrate. By a series of experiments, high oxide reliability resulting from a white ribbon-free nature, long lifetime from C-T measurement, and small leakage currents in a reverse biased p-n junction were obtained, as well as a small geometry structure. The feasibility of this technology for MOS LSI's were examined in a 3-/spl mu/m rule memory chip, and a reasonable yield and reliability were obtained. The physical limitations of SEPOX were also considered and submicrometer capability was confirmed.     

多晶硅发射极晶体管（PET）Gummel－Poon模型

本文建立了能直接用于ＳＰＩＣＥ电路分析程序中的ＰＥＴ－ＧＰ模型。研究表明：可以采用两种方法来使用ＰＥＴ－ＧＰ模型。本文利用所研究器件的结构参数计算了ＰＥＴ－ＧＰ模型参数β＿Ｆ和特征频率ｆ＿Ｔ，ｆ＿Ｔ的计算和实验结果符合较好。β＿Ｆ的计算表明，所研究器件的多晶硅／硅界面复合较强，复合速度Ｓ＿ｐ达到１０￣６ｃｍ／ｓ。     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

复合多晶硅双极晶体管DC～3 Gb/s LD/EA驱动器

本文介绍了一种新型LD/EA驱动器.该驱动器采用四个塑封NPN多晶硅双极晶体管和一个常规硅双极晶体管作为有源器件,可以在25Ω负载上产生50mA的调制电流用于直接驱动激光器或在50Ω负载上产生2.5V的调制电压用于驱动EA调制器.该驱动器的工作速率为DC至3Gb/s,调制电流和偏置电流调节范围分别为5～50mA,上升、下降时间小于100ps.     

A Simple Model of DIGBL Effect for Polysilicon Films and Polysilicon Thin-Film Transistors

Based on charge conservation assumption, analytical models of the drain-induced grain barrier lowering effect are developed for polysilicon films by 1-D Poisson's equation and for polysilicon thin-film transistors (poly-Si TFTs) by quasi-2-D Poisson's equation. It is shown that the voltage drop at the lower barrier side is less than that at the higher barrier side for both poly-Si films and poly-Si TFTs when applying a lateral bias across the grain-boundary barrier.     

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Design Considerations for Paralleling Bipolar Transistors

A simple design procedure for direct paralleling of bipolar junction transistors (BJT's) is proposed. It is based on the matching of transfer characteristics (Ic versus VCE) at a low collector voltage. The design procedure further addresses the base and collector circuit's layout requirements, optimal base-driven conditions, and thermal design requirements for reliable and efficient operation of BJT's in parallel. The influence of a snubber circuit is also discussed. The procedure is verified experimentally by performing dynamic and reversebias safe operating area (RBSOA) testings.     

双极晶体管的进步

尽管MOSFET已经成为众多电源管理设计者默认的选择,但是双极晶体管也一直是媒体关注的焦点,并且在某些电源开关应用中是更好的选择.近几年来,双极晶体管发展很快,并经历了几代技术上的进步.如图1所示. 本文首先综述当前双极晶体管的特性,然后说明它们不可或缺的优越性如何在实际中得到应用.     

多晶硅薄膜晶体管亚阈值区准二维模型(英文)

从准二维泊松方程出发,结合多晶硅扩散和热发射载流子输运理论,建立了多晶硅薄膜晶体管亚阈值电流模型。由表面势方程及亚阈值电流方程求得包含陷阱态和晶粒尺寸的亚阈值斜率解析表达式。模型具有简明的表达式,并且在大晶粒和低陷阱态情形下可简化为传统长沟道MOSFET亚阈值区模型。仿真结果与试验数据符合得很好,验证了模型的正确性。     

异质结双极型晶体管的能带设计

化合物半导体的液相外延技术,特别是近年来分子束外延(MBE)和金属有机化合物化学气相渡积(MOCVD)技术的进展,为半导体新器件的发展提供了良好的工艺基础.本文分析和讨论了在上述工艺基础上双极型晶体管的能带设计.其中包括宽发射极、宽收集极和能带宽度的设计.讨论了异质发射结附近能带尖峰和基区中速度过冲之间的联系与设计要点.提出了Auger晶体管的概念以及在工艺上如何实现的具体结构.文章最后以微波低噪声双极型晶体营为例,给出了一个具体的能带设计图.     

77K多晶硅发射区双极型晶体管

本文介绍了适于77K工作的多晶硅发射区双极型晶体管,给出了在不同工作电流条件下的电流增益的温度模型。结果表明在小电流条件下电流增益随温度下降而下降得更为剧烈,并且讨论了在不同注入情况下,浅能级杂质的陷阱作用对截止频率的影响。     

Silicon Bipolar Microwave Power Transistors

This paper presents a review of the present states of commercially available silicon bipolar transistors and projects what power at frequency performance will be available in the next few years. It discusses the need for implementing certain fabrication/processing developments necessary to meet the projected power at frequency performance Ievels.