A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design

We present a voltage mode switched-capacitor Field Programmable Analog Array (FPAA) to be used to implement various analog circuits. The FPAA consists of uniform configurable analog blocks (CABs) allowing implementation of different functions. Each CAB consists of two back-to-back connected inverting and non-inverting strays-insensitive switched-capacitor integrators. The interconnection between CABs is implemented by switched and unswitched capacitor networks. The internal structure of CABs and the interconnection between different CABs are configured by user-programmable digital control signals. The functionality of the FPAA is demonstrated through embedding of different types of filters, programmable amplifiers, biquads, modulators and signal generators along with simulation results.     

A CMOS field-programmable analog array

The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2-μm CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array     

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

Filter Design Using a New Field-Programmable Analog Array (FPAA)

We present a voltage mode switched-capacitor Field ProgrammableAnalog Array (FPAA) to be used to implement various filter structures.The FPAA consists of uniform configurable analog blocks (CABs)allowing implementation of different functions. Each CAB consistsof two back-to-back connected inverting and non-inverting strays-insensitiveswitched-capacitor integrators. The interconnection between CABsis implemented by switched and unswitched capacitor networks.The internal structure of CABs and the interconnection betweendifferent CABs are configured by user-programmable digital controlsignals. The functionality of the FPAA is demonstrated throughembedding of different types of filters along with simulationresults.     

Field-programmable analogue array design based on the wave active filter design method

In this paper, a new methodology for the design of field-programmable analogue arrays (FPAAs) is proposed based on the introduction of a new configurable analogue block (CAB), which is the key element for the design of FPAAs. This new CAB is based on the wave equivalents of passive, single-element two-ports. The proposed FPAA structures are versatile and very simple to design. In addition, due to the lack of the interconnection network common to other FPAA structures, the resulting structures employ a minimum number of switches in the signal path and exhibit high modularity.     

Field programmable analog arrays for implementation of generalized nth‐order operational transconductance amplifier‐C elliptic filters

This study presents a new architecture for a field programmable analog array (FPAA) for use in low‐frequency applications, and a generalized circuit realization method for the implementation of nth‐order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA‐C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA‐C symmetric balanced structure for even/odd‐nth‐order low‐pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low‐power designs for implementation of biopotential signal processing systems.     

Placement for large-scale floating-gate field-programable analog arrays

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPAA clustering algorithm first groups analog components into a set of clusters so that the total number of routing switches used is minimized and all IO paths are balanced in terms of routing switches used. Our FPAA placement algorithm then maps each cluster to a computational analog block (CAB) of the target FPAA while focusing on routing switch usage and balance again. Experimental results demonstrate the effectiveness of our approach.     

A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design

The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.     

Current follower based reconfigurable integrator/differentiator circuits with passive and active components׳ reuse

Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.     

A Current Conveyor based Field Programmable Analog Array

An approach for designing a Field Programmable Analog Array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An Analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. Analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

Built-in self-test of global interconnects of field programmable analog arrays

Strategies for the test of Field Programmable Analog Arrays (FPAAs) have been devised based on testing separately their main three components: configurable analog blocks, I/O pads and interconnection network. In this work, a scheme for testing the interconnection network, in particular the global wiring, is presented. As long as analog wiring is considered, catastrophic faults at the switches and wires are considered, as well as parametric capacitive or resistive defects in interconnects. Similarly to FPGAs, critical path search is based on a graph model, so that known algorithms are reused, yielding a minimum number of Test Configurations. Then, a near-zero area overhead BIST procedure is proposed, in which Analog Built-in Block Observers are implemented as oscillators and integrators, respectively, generating test stimuli and analyzing output responses, using internal configurable resources of the FPAA.     

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.     

A High-Frequency Field-Programmable Analog Array (FPAA) Part 2: Applications

This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.     

Flexibility of interconnection structures for field-programmablegate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

自由空间二维榕树网实现方法

鉴于榕树网在自由空间光子交换网络中具有重要的应用价值,分析了榕树网的特点和4×4二维榕树网的空间拓扑结构,通过偏振光分光棱镜、微闪耀光栅阵列、平面反射镜、半反半透镜和液晶空间光调制器的集成,构建二维的榕树交换网实验模块,利用微闪耀光栅的衍射特性,控制每块微闪耀光栅的周期,以实现入射光信号不同方向的闪耀输出,最终完成二维榕树网自由空间水平和竖直方向上的交叉互连,直通则由平面镜反射实现。对二维榕树网实验模块的功能分析表明,该实验模块理论上可以完成4×4二维面阵内光信号(或数据)的排序、交换、组播、广播、矩阵变换等操作,具有交换透明、速度快、空间带宽高等特点,在全光交换和光通信中具有一定的应用。     

Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme

Since the 1970's, the analog switches in switched-capacitor (SC) circuits are operated by nonoverlapping bi-phase control signals (/spl phi//sub 1/, /spl phi//sub 2/). The nonoverlapping of these two phases is essential for successful SC operation since, a capacitor inside an SC circuit can discharge if two switches, driven by /spl phi//sub 1/ and /spl phi//sub 2/, are turned on simultaneously. Moreover, since 1983, two additional phases are generally used in many SC circuits, which consist of advanced versions of /spl phi//sub 1/ and /spl phi//sub 2/. These two additional phases overcome the problem of signal-dependent charge injection. This paper presents a low-power and low-voltage analog-to-digital (A/D) interface module for biomedical applications. This module provides an A/D conversion based on a mixed clock-boosting/switched-opamp (CB/SO) second-order sigma-delta (/spl Sigma//spl Delta/) modulator, capable of interfacing with several different types electrical signals existing in the human body, only by re-programming the output digital filter. The proposed /spl Sigma//spl Delta/ architecture employs a novel single-phase scheme technique, which improves the dynamic performance and highly reduces the clocking circuitry complexity, substrate noise and area. Simulated results demonstrate that the signal integrity can be preserved by exploring the gap between the high conductance region of pMOS and nMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. The mixed CB/SO architecture together with the overall distortion reduction resulting from using the proposed single-phase scheme, result that the dynamic range of the modulator is pushed closer to the theoretical limit of an ideal second-order /spl Sigma//spl Delta/ modulator.     

A new current-mode computational analog block free from the body-effect

In this paper, a new computational/configurable analog block (CAB) is presented based on MOS translinear (MTL) for current-mode nonlinear computation. The proposed CAB architecture consists of three main structures: a new MTL cell, NMOS-PMOS arrays, and two local switch networks. As the new trait, it benefits from an effective compensation technique that extensively minimizes the error generated by body effect–the most important factor amongst the second-order effects. The second feature is that the MTL cell only with six transistors has enabled the CAB to implement more arithmetic functions. This block is capable of implementing such various nonlinear functions as squaring, inverse function, N-dimensional vector summation, full-wave rectifier, four-quadrant multiplier/divider, two-quadrant square-root, and exponential functions. The proposed CAB is simulated with CADENCE and HSPICE software in 0.18 μm TSMC CMOS technology at 1.8 V supply voltage. Most importantly, Post-layout plus Monte Carlo, corner case, and temperature variation simulations are performed to investigate its robust performance in the presence of PVT fabrication non-idealities. Functionality and flexibility of the proposed CAB make it suitable for the core block of Field-Programmable Analog Array (FPAA) ICs and signal processing applications.