Thermal modeling and measurement of AlGaN-GaN HFETs built on sapphire and SiC substrates

We present thermal modeling and measurement results of AlGaN-GaN heterojunction field effect transistors fabricated on sapphire and SiC substrates, respectively. The device structures are identical except for the substrate material used to grow the AlGaN-GaN heterostructure. One objective is to study the effect of substrate material on the thermal and electrical performance of the resulting devices. To compute the temperature profiles, in-house PAMICE code developed for a three-dimensional structure was used. To measure the temperatures on the chip surface, nematic liquid crystal thermography was used. This technique is nondestructive and can be performed in realtime during device operation. It has submicrometer spatial resolution and /spl plusmn/1/spl deg/C temperature accuracy. The measured temperatures agree well with the calculated ones. The relationship between the measured temperature and power is almost linear for both types of devices. The junction-to-case thermal resistance of the device fabricated on sapphire substrate is 4.4 times that of the device built on SiC substrate.     

Thermal analysis of AlGaN-GaN power HFETs

In this paper, we present a thermal analysis of AlGaN-GaN power heterojunction field-effect transistors (HFETs). We report the dc, small-signal, large-signal, and noise performances of AlGaN-GaN HFETs at high temperatures. The temperature coefficients measured for GaN HFETs are lower than that of GaAs pseudomorphic high electron-mobility transistors, confirming the potential of GaN for high-temperature applications. In addition, the impact of thermal effects on the device dc, small-signal, and large-signal characteristics is quantified using a set of pulsed and continuous wave measurement setups. Finally, a thermal model of a GaN field-effect transistor is implemented to determine design rules to optimize the heat flow and overcome self-heating. Arguments from a device, circuit, and packaging perspective are presented.     

High-yield flip-chip bonding and packaging of low-threshold VCSEL arrays on sapphire substrates

Oxide-confined top-emitting 850 nm and bottom-emitting 980 nm vertical-cavity surface-emitting laser (VCSEL) 8/spl times/8 arrays were designed and fabricated for applications of optical interconnects. The arrays were flip-chip bonded onto sapphire substrates that contain complimentary metal-oxide-semiconductor (CMOS) driver and fan-out circuitries. The off-sited bonding contacts and minimized bonding force produced very high yield of the hybridization process without causing damage to the VCSEL mesas. The hybridized devices were further mounted either on printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical outputs from the top-emitting VCSEL arrays to transmit directly through without additional substrate removal procedure. Lasing thresholds below 250 /spl mu/A for 850 nm VCSELs and 800 /spl mu/A for 980 nm VCSEL were found at room temperature. The oxide confinement apertures of VCSELs were measured to be around 6 /spl mu/m in diameter. High-speed data transmission demonstrated a bandwidth of up to 1 Gbits/s per channel for these hybridized VCSEL transmitters.     

12 W/mm AlGaN-GaN HFETs on silicon substrates

Al/sub 0.26/Ga/sub 0.74/N-GaN heterojunction field-effect transistors were grown by metal-organic chemical vapor deposition on high-resistivity 100-mm Si (111) substrates. Van der Pauw sheet resistance of the two-dimensional electron gas was 300 /spl Omega//square with a standard deviation of 10 /spl Omega//square. Maximum drain current density of /spl sim/1 A/mm was achieved with a three-terminal breakdown voltage of /spl sim/200 V. The cutoff frequency and maximum frequency of oscillation were 18 and 31 GHz, respectively, for 0.7-/spl mu/m gate-length devices. When biased at 50 V, a 2.14-GHz continuous wave power density of 12 W/mm was achieved with associated large-signal gain of 15.3 dB and a power-added efficiency of 52.7%. This is the highest power density ever reported from a GaN-based device grown on a silicon substrate, and is competitive with the best results obtained from conventional device designs on any substrate.     

Source resistance reduction of AlGaN-GaN HFETs with novel superlattice cap layer

We have developed a novel AlGaN-GaN heterojunction field effect transistor (HFET) with an ultralow source resistance by employing the novel superlattice (SL) cap structure. The particular advantage of the SL cap, i.e., the existence of multiple layers of the polarization-induced two-dimensional electron gas (2DEG) with high mobility and high concentration at each AlGaN-GaN interface, is fully exploited for lowering the lateral resistance and the potential barrier at the interface of the SL cap and the HFET barrier layer. By designing the AlGaN-GaN thickness ratio, we have established a method to obtain the optimized SL structure and have achieved an extremely low source resistance of 0.4 /spl Omega//spl middot/mm which is lower not only than HFETs with the conventional structure but also than those with the n-GaN cap structure. The SL cap HFET fabricated on a sapphire substrate exhibited excellent dc and RF performance, i.e., maximum transconductance of over 400 mS/mm, maximum drain current of 1.2 A/mm, a cutoff frequency of 60 GHz, a maximum frequency of oscillation of 140 GHz, and a very low noise figure minimum of 0.7 dB at 12 GHz.     

The improvement of DC performance in AlGaN-GaN HFETs with isoelectronic Al-doped channels

Enhancement of electrical properties of an AlGaN-GaN heterostructure was achieved through isoelectronic Al-doping of the undoped channel layer during the growth by metal-organic chemical vapor deposition. The two-dimensional electron gas mobility was increased from 3390 to 4870 cm/sup 2//V/spl middot/s at 77 K, and the crystal quality was significantly improved as Al atoms were incorporated in the undoped GaN film. The AlGaN-GaN HFETs were fabricated on this material structure and exhibited a maximum drain current of 909 mA/mm, and a maximum transconductance of 232 mS/mm, corresponding to an increase of 30% and 21%, respectively.     

Polyimide passivated AlGaN-GaN HFETs with 7.65 W/mm at 18 GHz

Current metal-organic chemical vapor deposition-grown AlGaN-GaN heterojunction field-effect transistor devices suffer from threading dislocations and surface states that form traps, degrading RF performance. A passivation scheme utilizing a polyimide film as the passivating layer was developed to reduce the number of surface states and minimize RF dispersion. Continuous-wave power measurements were taken at 18 GHz on two-finger 0.23-/spl mu/m devices with 2/spl times/75 /spl mu/m total gate width before and after passivation yielding an increase from 2.14 W/mm to 4.02 W/mm in power density, and 12.5% to 24.47% in power added efficiency. Additionally, a 2/spl times/25 /spl mu/m device yielded a peak power density of 7.65 W/mm at 18 GHz. This data suggests that polyimide can be an effective passivation film for reducing surface states.     

Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier Layers

The effect of SiN surface passivation by catalytic chemical vapor deposition (Cat-CVD) on Al/sub 0.4/Ga/sub 0.6/N-GaN heterostructure field-effect transistors (HFETs) was investigated. The channel sheet resistance was reduced by the passivation due to an increase in electron density, and the device characteristics of the thin-barrier HFETs were significantly improved by the reduction of source and drain resistances. The AlGaN(8 nm)-AlN(1.3 nm)-GaN HFET device with a source/drain distance of 3 /spl mu/m and a gate length of 1 /spl mu/m had a maximum drain current density of 0.83 A/mm at a gate bias of +1.5 V and an extrinsic maximum transconductance of 403 mS/mm. These results indicate the substantial potential of Cat-CVD SiN-passivated AlGaN-GaN HFETs with thin and high Al composition barrier layers.     

Enhanced-performance of AlGaN-GaN HEMTs grown on grooved sapphire substrates

We report significantly improved dc characteristics and RF performance of AlGaN-GaN HEMTs grown on grooved sapphire substrates. Grooves 60 nm deep with 2-/spl mu/m-wide ridges and 4-/spl mu/m-wide trenches were created along the <101~0> orientation of the substrate by inductively coupled-plasma reactive ion etching. Device mesas were defined over the trench regions where superior crystalline quality was observed by other characterization techniques. Compared to conventional HEMTs grown on the planar area, the devices on the grooved substrate show increased drain saturation current and peak transconductance. Their reverse gate leakage current is over three orders of magnitude lower. These devices also show increased off-state breakdown voltage with hard breakdown characteristics. For nominal 1-/spl mu/m-gate-length HEMTs, the best current gain and power gain cutoff frequencies were 15 and 54 GHz, respectively. The on-wafer output power, gain, and power-added efficiency of an unpassivated device measured at 4 GHz were 3.26 W/mm, 25.7 dB, and 55.6%. The enhanced performance is attributed to low-density mixed dislocations and high crystalline quality over the trench regions.     

Blue flip-chip AlGaInN LEDs with removed sapphire substrate

Characteristics of AlGaInN LEDs with removed sapphire substrate are studied. To remove the substrate from a finished LED crystal mounted by the flip-chip method onto a silicon wafer, the laser lift-off technique was used. To raise the light output efficiency, a scattering profile was formed on the n-GaN surface by ion etching in a Cl₂: Ar gas mixture. This resulted in the 25–30% increase in the external quantum efficiency of LEDs. The LEDs fabricated in this way demonstrate stable operation at drive currents of up to 300 mA with an optical power as high as 110 mW.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Development of no-flow underfill materials for lead-free solderbumped flip-chip applications

No-flow underfill process in flip-chip assembly has become a promising technology toward a smaller, faster and more cost-efficient packaging technology. The current available no-flow underfill materials are mainly designed for eutectic tin-lead solders. With the advance of lead-free interconnection due to the environmental concerns, a new no-flow underfill chemistry needs to be developed for lead-free solder bumped flip-chip applications. Many epoxy resin/hexahydro-4-methyl phthalic anhydride/metal acetylacetonate material systems have been screened in terms of their curing behavior. Some potential base formulations with curing peak temperatures higher than 200°C (based on differential scanning calorimetry at a heating rate of 5°C/min) are selected for further study. The proper fluxing agents are developed and the effects of fluxing agents on the curing behavior and cured material properties of the potential base formulations are studied using differential scanning calorimetry, thermomechanical analysis, dynamic-mechanical analysis, thermogravimetric analysis, and rheometer. Fluxing capability of the developed no-flow formulations is evaluated using the wetting test of lead-free solder balls on a copper board. The developed no-flow underfill formulations show sufficient fluxing capability and good potential for lead-free solder bumped flip-chip applications     

Inductance-controlled electroabsorption Modulator modules using the flip-chip bonding technique

The wire-bonding technique is widely used for the connections between the electroabsorption (EA) modulator chips and the electrical signal transmission lines. However, the parasitic inductance of the bonding wire degrades the electrical characteristics of the EA modulator modules in a high-frequency region. In this paper, we theoretically analyze the influence of parasitic inductance on the base-band digital transmission and obtain the relationship between the EA modulator capacitance and the optimum lead inductance. For precise inductance control, we introduced the flip-chip bonding (FCB) technique and fabricated 40-Gb/s EA modulator modules.     

A new flip-chip bonding technique using micromachined conductivepolymer bumps

Using micromachining techniques with thick photoresists, a new conductive polymer flip-chip bonding technique that achieves both a low processing temperature and a high bumping alignment resolution has been developed in this work. By the use of UV-based photolithography with thick photoresists, molds for the flip-chip bumps have been patterned, filled with conductive polymers, and then removed, leaving molded conductive polymer bumps. After flip-chip bonding with the bumps, the contact resistances measured for 25 μm-high bumps with 300 μm×300 μm area and 400 μm×400 μm area were 35 mΩ and 12 mΩ respectively. The conductive polymer flip-chip bonding technique developed in this work shows a very low contact resistance, simple processing steps, a high bumping alignment resolution (<±5 μm), and a lower bonding temperature (~170°C). This new bonding technique has high potential to replace conventional flip-chip bonding technique for sensor and actuator systems, bio/chemical μ-TAS, optical MEMS, OE-MCM's, and electronic system applications     

In process stress analysis of flip-chip assemblies during underfill cure

Low cost flip chip on board assemblies are analyzed during the underfill cure process to determine residual stress generation. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip-chip test vehicles, based on the Sandia National Laboratories’ ATC04 assembly test chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented with respect to the residual stresses produced by each underfill on the flip-chip assemblies. Significant stress variations are observed between the four underfills studied. Correlation between the glass transition temperature (T_g) and storage modulus (G^′) are made relative to residual stresses produced during underfill cure. Stress relaxation characteristics are also evaluated for the low cost flip-chip assemblies.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Modeling of the curing kinetics of no-flow underfill in flip-chip applications

No-flow underfill has greatly improved the production efficiency of flip-chip process. Due to its unique characteristics, including reaction latency, curing under solder reflow conditions and the desire for no post-cure, there is a need for a fundamental understanding of the curing process of no-flow underfill. Starting with a promising no-flow underfill formulation, this paper seeks to develop a systematic methodology to study and model the curing behavior of this underfill. A differential scanning calorimeter (DSC) is used to characterize the heat flow during curing under isothermal and temperature ramp conditions. A modified autocatalytic model is developed with temperature-dependent parameters. The degree of cure (DOC) is calculated; compared with DSC experiments, the model gives a good prediction of DOC under different curing conditions. The temperature of the printed wiring board (PWB) during solder reflow is measured using thermocouples and the evolution of DOC of the no-flow underfill during the reflow process is calculated. A stress rheometer is used to study the gelation of the underfill at different heating rates. Results show that at high curing temperature, the underfill gels at a lower DOC. Based on the kinetic model and the gelation study, the solder wetting behavior during the eutectic SnPb and lead-free SnAgCu reflow processes is predicted and confirmed by the solder wetting tests.     

An improvement of thermal conductivity of underfill materials for flip-chip packages

Effective heat dissipation is crucial to enhance the performance and reliability of electronic devices. In this work, the performance of encapsulants filled with carbon fiber was studied and compared with silica filled encapsulants. Encapsulants filled with mixed combination of fillers for optimizing key properties were also investigated. The thermal and electrical conductivities were investigated and glass transition temperature (Tg), thermal expansion coefficient (TCE), and storage modulus (E') of these materials were studied with thermal analysis methods. The composites filled with both carbon fiber and silica showed an increase of thermal conductivity three to five times of that of silica filled encapsulants of the same filler loading while maintaining/enhancing major mechanical and thermal properties.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.