Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Rapid isothermal annealing of high- and low-energy ion-implantedInP and In0.53Ga0.47As

Rapid isothermal annealing (RIA) was performed on 0.5-16-MeV Si ⁺, 1-MeV Be⁺, and 150-keV Ge⁺ implanted InP:Fe and 380-keV Fe⁺ implanted InGaAs. Annealings were performed in the temperature range 800-925°C using an InP proximity wafer in addition to the Si₃N₄ dielectric cap. Dopant activations close to 100% were obtained for 3×10¹⁴ cm^-2 Si⁺ and 2×10¹⁴ cm^-2 Be⁺ implants in InP:Fe. For the elevated temperature (200°C) 1×10¹⁴ cm^-2 Ge⁺ implant, a maximum of 50% activation was obtained. No redistribution of dopant was observed for Si and Ge implants due to annealing. However, redistribution of dopant was seen for Be and Fe implants due to annealing. Phosphorous coimplantation has helped to eliminate the Be in-diffusion problem in InP, but did not help to reduce Fe in-diffusion and redistribution in InGaAs. Using an RIA cycle with low temperature and short duration is the only solution to minimize Fe redistribution in InGaAs     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Au/Pt/Ti/Ni ohmic contacts to p-ZnTe

Ohmic contacts of Au/Pd/Ti/Ni to p-ZnTe show a minimum specific contact resistance of 10^-6 Ωcm² for a p-type doping level of 3×10¹⁹ cm^-3 and at an annealing temperature of 300°C. The Ni and Ti layers are very effective in improving the electrical properties of these contact     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Shallow p+n junctions formed by using a two-stepannealing scheme with low thermal budget

Shallow p⁺n junctions have been formed by directly implanting BF₂ dopant into the Si substrate and then treating the samples by an annealing scheme with low thermal budget. A junction leakage smaller than 10 nA/cm² can be achieved by an annealing scheme that employs low-temperature long-time furnace annealing (FA) at 600°C for 3 h followed by medium-temperature rapid thermal annealing (RTA) at 800°C for 30 s. No considerable dopant diffusion is observed by using this low-thermal-budget annealing process. In addition, a moderate low-temperature annealing time of about 2-3 h should be employed to optimize the shallow p⁺n junction formed by this scheme. However, the annealing process that employs medium-temperature RTA followed by low-temperature FA treatment produces worse junctions than the annealing scheme that employs long-time FA at 600°C followed by RTA at 800°C     

Impact of nitrogen (N2+) implantation intopolysilicon gate on thermal stability of cobalt silicide formed onpolysilicon gate

A novel process which uses N₂⁺ implantation into polysilicon gates to suppress the agglomeration of CoSi₂ in polycide gated MOS devices is presented. The thermal stability of CoSi₂/polysilicon stacked layers can be dramatically improved by using N₂⁺ implantation into polysilicon. The sheet resistance of the samples without N₂⁺ implantation starts to increase after 875°C RTA for 30 s, while the sheet resistance of CoSi₂ film is not increased at all after 950 and 1000°C RTA for 30 s if the dose of nitrogen is increased up to 2×10¹⁵ cm^-2 and 6×10¹⁵ cm², respectively, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed. It is found that the transformation to CoSi₂ from CoSi is impeded by N₂⁺ implantation such that the grain size of CoSi₂ with N₂⁺ implantation is much smaller than that without N₂⁺ implantation. As a result, the thermal stability of CoSi₂ is significantly improved by N₂⁺ implantation into polysilicon     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

Gain measurement and upconversion analysis in Tm3+, Ho3+ co-doped alumino-zirco-fluoride glass

The small signal gain coefficients were measured in Tm³⁺,Ho³⁺ co-doped alumino-zirco-fluoride glass. A gain of 15%/cm at 2.05 μm was obtained for pump power density of 42 kW/cm². The temperature increase of the glass was found to be more than 150 K with this pump power, which was estimated from a comparison between fluorescence intensities of Tm^{3+ 3} F₄-³H₆ and Ho^{3+ 5} I₇-⁵I₈. An upconversion rate constant of 12.5×10^-17 cm³ sec^-1 from a coupled (Tm^{3+ 3}F₄, Ho^{3+ 5}I₇) level to a coupled (Tm^{3+ 3}H₅, Ho^{3+ 5}I₆) level was determined by fitting the experimentally obtained gain coefficients to the calculated one which takes into consideration any temperature increase     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

In-situ low energy BF2+ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF2+ in silicon molecular beam epitaxy (MBE) is described. BF2+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF2+-doped epitaxial material showed hard reverse breakdown characteristics.     

Junction depth versus sheet resistivity in BF2+-implanted rapid-thermal-annealed silicon

Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (junction depth) × (sheet resistivity)rho_{s}X_{j}has a smaller value with increasing implant dose and anneal temperature (boron solubility), and decreasing implant energy. However, the value is saturated for higher doses than 10¹⁶Xjcm², where Xjis junction depth in micrometers, and anneal temperature should be lower than 1100°C, because of considerable boron diffusion even in 10-s RTA.rho_{s}X_{j} = 18Ω.µm is achieved by BF2+ implantation with 5 × 10¹⁵-cm^-2dose at 30 keV and 1000°C RTA. The possibility of further improvement inrho_{s}X_{j}value is discussed.