基于迭代序的流程序局部性分析和优化

流编程模型是一种近年来被广泛研究的并行编程模型,它在基于软件管理的流式存储器,如流寄存器文件的流体系结构上得到了良好的应用.但同时也有研究指出流编程模型同样适合于基于硬件管理的一致性cache的体系结构.流编程模型目前最重要的应用背景GPGPU在发展中也逐渐引入通用的数据cache,因此发掘流程序的cache局部性就成为在这类体系结构上提高流程序性能的关键.由于流程序特殊的执行模型,其重用向局部性转化的过程与传统的串行程序不一致,无法直接使用传统的局部性分析方法直接对流程序进行分析.在深入分析了重用向局部性转化过程的基础上,提出了"迭代序"的概念用于描述流和串行程序重用向局部性转化时的不同,同时结合流程序的执行特点面向并行扩展了传统的局部性分析理论,给出了基于迭代序的局部性分析方法.此外,结合局部性分析模型还提出了两种流程序的cache局部性优化方法.在GPGPUSim模拟平台上进行的验证结果表明对流程序局部性的定量分析是有效的,并且提出的优化方法也可以有效改善流程序的cache局部性,提高流程序的性能.     

一种面向异构众核处理器的并行编译框架

异构众核处理器是面向高性能计算领域处理器发展的重要趋势,但其更为复杂的体系结构使得编程难的问题更加突出.针对这一问题,基于开源编译器Open64,提出了一种面向异构众核处理器的并行编译框架,将程序自动转换为异构并行程序.该框架主要包括4个模块：任务划分模块用来识别适合进行加速计算的程序段,实现了嵌套循环的多维并行识别方法;数据布局模块完成数据在主存和SPM之间的布局,实现了数组边界分析和指针范围分析;传输优化模块实现了数据传输合并、传输外提、打包传输、数组转置等多种数据传输优化方法;收益评估模块在构建代价模型的基础上实现了一种动静结合的收益评估方法.并且,基于SW26010处理器,对该编译框架进行了实现,测试结果表明,该编译框架能够实现一些程序以面向异构众核结构的并行变换,且获得较好的加速效果.     

面向申威异构架构的并行代码自动生成

异构架构逐渐成为高性能计算领域的主流架构,但相较于同构多核架构,其硬件结构及存储层次更为复杂,程序编写更为困难.先进的优化编译器可以协助程序开发人员实现更为高效的代码,降低程序开发复杂度.多面体编译模型通过抽象分析将程序抽象成空间多面体表示形式,能够将多种循环变换与硬件映射相结合,并面向特定体系结构生成相应的代码.设计实现了一个面向国产申威异构架构的并行代码自动生成系统,采用“源-源”编译模式,基于多面体编译模型实现.系统针对申威异构架构特点将程序计算过程进行硬件部署,同时实现数据传输与内存空间的自动管理.实验基于Polybench测试集中线性代数相关用例进行测试.结果表明,利用代码自动生成系统生成的异构并行代码能够在申威异构平台上正确运行,并能够有效发挥申威异构平台的性能,基于申威异构平台利用64线程加速计算的平均加速比达到了539.16倍.     

一种基于局部性的数据重组框架

处理器和内存之间速度差距日益增大,使内存访问成为系统主要的性能瓶颈之一,Cache成为现代体系结构中用来解决这个问题的主要技术.利用数据重组优化程序自身的局部性,从而提高Cache性能成为一个值得研究的热点问题.提出了一种基于局部性的数据重组框架,该框架利用一种基于变量局部性特征的变量关系图来量化变量之间的关系,然后寻找变量之间的布局优化,通过数据重组和结构拆分两种常用的数据重组方法来提高Cache性能.针对SPEC CPU2000中的部分测试程序的实验表明,这种数据重组框架能够有效地减少Cache失效次数,提高程序性能.     

D-S证据下的高铁信号系统异构数据融合

针对当前高速铁路信号系统数据信息多源异构问题,提出一种新的高铁信号异构数据融合框架设计方案.利用本体思想和D-S证据理论方法,对底层数据信息进行特征融合,减少数据冗余,提高数据质量,优化决策效率,进行实验验证.实验结果表明:该方法在一定规模数据量时,计算速度快且准确率高,所提出的新的异构数据融合架构可行,融合算法有效.     

基于数据重用分析的多面体循环合并策略

现有多面体编译工具往往使用一些简单的启发式策略来寻找最优的语句合并,对于不同的待优化程序,需要手工调整循环合并策略以获得最佳性能.针对这一问题,面向多核CPU目标平台,文中提出了一种基于数据重用分析的循环合并策略.该策略避免了不必要的且会影响数据局部性利用的合并限制:针对调度的不同阶段,提出了面向不同并行层次的并行性合并限制;对于数组访问关系较为复杂的语句,提出了面向CPU高速缓存优化的分块性合并限制.相较于以往的合并策略,该策略在计算合并收益时考虑到了空间局部性的变化.文中基于LLVM编译框架中的多面体编译模块Polly实现了这一策略,并选用Polybench等测试套件中的部分测试用例进行测试.实验结果表明,相较于现有的多种合并策略,在单核执行情况下,测试用例平均获得了14.9％～62.5％的性能提升;在多核执行情况下,多个测试用例平均获得了19.7％～94.9％的性能提升,在单个测试用例中最高获得了1.49x～3.07x的加速效果.     

OpenMP数据分布子句自动生成算法

将OpenMP程序扩展到异构多核结构时,非本地存储访问会导致访存开销增加,影响程序性能。针对该问题,引入带数组划分信息的数据分布子句,对数据在异构多核存储系统的布局进行管理,提出一种基于并行循环识别和数组引用模式分析的算法,实现该类子句的自动生成。实验结果表明,自动生成的OpenMP程序包含数据分布子句,具有较好的数据局部性,可降低访存开销,在异构多核系统上获得明显的性能提升。     

基于“嵩山”超级计算机系统的大规模管网仿真

供水管网仿真广泛应用于城市供水输配调度,是城市供水管网监测与维护的重要技术手段。由于在面向城市级的大规模管网中产生了海量的计算数据,因此在一般计算平台上无法满足管网仿真计算的算力需求。为提升城市级供水管网仿真的计算效率,提出一种有效的并行化方案。基于“嵩山”超级计算机系统采用中央处理器+数据缓存单元（CPU+DCU）架构,利用其在密集数据计算方面的优势,对“嵩山”超级计算机进行供水管网仿真。参照可移植性异构计算接口（HIP）异构编程模型,在“嵩山”超级计算机上实现供水管网仿真的异构计算,并结合管道数据分割方案,使用消息传递接口开启多进程以实现DCU加速数据通信传递。通过重定义数据类型解决计算过程中结构体传输问题,实现单节点内多DCU的大规模密集计算。在不同计算平台和多种计算策略仿真上的对比结果表明,与传统x86平台相比,该优化方案在小规模数据与大规模数据上的加速比分别达到5.269、10.760,与采用计算统一设备架构异构编程模型的传统GPU异构平台相比,计算性能有明显提高。     

面向多核集群的数据流程序层次流水线并行优化方法

数据流编程语言是一种面向领域的编程语言,它能够将计算与通信分离,暴露应用程序的并行性.多核集群中计算、存储和通信等底层资源的复杂性对数据流程序的性能提出了新的挑战.针对数据流程序在多核集群上执行存在资源利用低和扩展性差等问题,利用同步数据流图作为中间表示,文中提出并实现了面向多核集群的层次性流水线并行优化方法.方法包含任务划分与调度、层次流水线调度和数据局部性优化,经过编译优化后生成基于MPI的可并行执行的目标代码.其中任务划分与调度是利用程序中数据和任务并行性将任务映射到计算核上,实现负载均衡和低通信同步开销;层次性流水线调度是利用程序中的并行性构造低延迟流水线调度;数据局部性优化是针对数据访问存在的Cache伪共享做面向存储的优化.实验以X86架构多核处理器组成的集群为平台,选取媒体处理领域的典型应用算法作为测试程序,对层次流水线优化进行实验分析.实验结果表明了优化方法的有效性.     

基于异构多核的CCA并行构件模型

并行构件技术的出现提高了并行软件的开发效率,但现有的并行构件技术缺乏对异构多核平台的支持.为了提高并行构件程序在异构平台上的执行性能,扩展CCA(通用构件体系结构)并行构件模型支持CCA异构并行构件,提出了一种异构的CCA并行构件模型.使用管理者—工人模式调度CCA异构并行构件内的计算任务到异构多核平台上加速执行.在CCA构件工具包的基础上实现了支持扩展CCA并行构件模型的编译系统和运行时框架.在CELL BE和GPU两种异构多核处理器上进行的实验证明了提出的方法比原始的CCA构件程序具有较优的性能.提出的并行构件模型应用在并行程序开发中可以提高并行程序的性能.     

Locality principle revisited: A probability-based quantitative approach

This paper revisits the fundamental concept of the locality of references and proposes to quantify it as a conditional probability: in an address stream, given the condition that an address is accessed, how likely the same address (temporal locality) or an address within its neighborhood (spatial locality) will be accessed in the near future. Previous works use reuse distance histograms as a measure of temporal locality. For spatial locality, some ad hoc metrics have been proposed as a quantitative measure. In contrast, our conditional probability-based locality measure has a clear mathematical meaning and provides a theoretically sound and unified way to quantify both temporal and spatial locality. We showcase that our quantified locality measure can be used to evaluate compiler optimizations, to analyze the locality at different levels of memory hierarchy, to optimize the cache architecture to effectively leverage the locality, and to examine the effect of data prefetching mechanisms.     

Cacheminer: A runtime approach to exploit cache locality on SMP

Exploiting cache locality of parallel programs at runtime is a complementary approach to a compiler optimization. This is particularly important for those applications with dynamic memory access patterns. We propose a memory-layout oriented technique to exploit cache locality of parallel loops at runtime on Symmetric Multiprocessor (SMP) systems. Guided by application-dependent and targeted architecture-dependent hints, our system, called Cacheminer, reorganizes and partitions a parallel loop using the memory-access space of its execution. Through effective runtime transformations, our system maximizes the data reuse in each partitioned data region assigned in a cache, and minimizes the data sharing among the partitioned data regions assigned to all caches. The executions of tasks in the partitions are scheduled in an adaptive and locality-presented way to minimize the execution time of programs by trading off load balance and locality. We have implemented the Cacheminer runtime library on two commercial SMP servers and an SimCS simulated SMP. Our simulation and measurement results show that our runtime approach can achieve comparable performance with the compiler optimizations for programs with regular computation and memory-access patterns, whose load balance and cache locality can be well optimized by the tiling and other program transformations. However, our experimental results show that our approach is able to significantly improve the memory performance for the applications with irregular computation and dynamic memory access patterns. These types of programs are usually hard to optimize by static compiler optimizations     

Compiler-Directed Code Restructuring for Improving Performance of MPSoCs

One of the critical goals in code optimization for multi-processor-system-on-a-chip (MPSoC) architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles. While conventional data locality optimization techniques can be used for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the on-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block. In order to test the effectiveness of our approach, we implemented it using a publicly-available compiler infrastructure and conducted experiments with twelve data-intensive embedded applications. Our results show that optimizing data locality for shared data elements is very useful in practice.     

FORALL实现过程中的局部性优化

FORALL结构是FORTRAN 95的一种语法,在编译器中高效地实现FORALL结构是一项富有挑战性的工作,局部性优化对其高效实现尤其重要。本文介绍作者在G95编译器中实现FOR ALL结构时用到的两种局部性优化方法--临时空间合并和嵌套循环排序。实验结果表明,局部性优化对提高FORALL结构的性能非常有效。对某类FORALL结构,与Intel的EFC 编译器相比,我们的实现方法能提高30％的性能。     

Compiler techniques for the distribution of data and computation

This paper presents a new method that can be applied by a parallelizing compiler to find, without user intervention, the iteration and data decompositions that minimize communication and load imbalance overheads in parallel programs targeted at NUMA architectures. One of the key ingredients in our approach is the representation of locality as a locality-communication graph (ICG) and the formulation of the compiler technique as a mixed integer nonlinear programming (MINLP) optimization problem on this graph. The objective function and constraints of the optimization problem model communication costs and load imbalance. The solution to this optimization problem is a decomposition that minimizes the parallel execution overhead. This paper summarizes the process of how the compiler extracts the locality information from a nonannotated code and focuses on how this compiler can derive the optimization problem, solve it, and generate the parallel code with the automatically selected iteration and data distributions. In addition, we include a discussion about our model and the solutions - the decompositions - that it provides. The approach presented in the paper is evaluated using several benchmarks. The experimental results demonstrate that the MINLP formulation does not increase compilation time significantly and that our framework generates very efficient iteration/data distributions for a variety of NUMA machines.     

An Energy-Efficient Processor Architecture for Embedded Systems

We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.     

一种基于线性代数的计算和数据自动分解算法

在针对分布内存体系结构的并行识别技术中，如何对计算和数据进行合理分解，以增加数据引用的本地化、减少处理器间的通信是提高并行程序性能的关键。本文通过对Anderson-lam分解算法完整性的补充，给出了一种可实现无通信的计算划分和数据分布算法，并阐述了对该算法在工程实践中的一些优化考虑。     

面向OpenMP和OpenTM应用的并行数据重用理论

将经典的数据重用理论扩充到并行领域,分别提出了面向OpenMP和OpenTM应用的并行数据重用理论.针对重用在线程、事务中的关系,系统地讨论了并行应用中重用的分类、判定和求解方法.同时,应用这一理论研究了OpenTM循环的优化技术,以降低事务被回退的风险.最后,使用并行数据重用理论分析和统计了SPEComp2001中的数据重用.并行数据重用理论可以用于指导面向多核存储共享结构的并行程序分析和编译优化技术研究.     

面向国产异构众核系统的Parallel C语言设计与实现

异构众核架构具有超高的性能功耗比,已成为超级计算机体系结构的重要发展方向.但众核系统更为复杂的并行层次和存储层次,给编程和优化带来了极大的挑战,因此研究面向众核系统的并行编程技术,对于降低国产众核系统并行应用的编程难度、提升并行程序的性能都具有重要的意义.提出统一架构的多模式并行编程模型,包括异构融合的加速运算模型和按同构方式编程的自主运算模型,根据编程模型设计了Parallel C语言,能有效描述国产众核系统的异构并行性,与其它众核系统上MPI+X的使用模式相比,编程和系统优化都具有全局视角,在多级局部性描述、单边消息、兼容已有多核应用等方面具有特色;基于Open64构建了Parallel C编译系统,全面支持加速运算模型和自主运算模型,提出并实现了数据布局与自动DMA、编译指导的线程代理和拓扑位置感知的集合通信等优化.Micro Benchmark和实际应用在神威太湖之光计算机系统上的测试数据表明,Parallel C语言和编译系统具有良好的性能和可扩展性,能够有效支撑大型应用.     

Arranging statements and data of program instances for locality

In memory hierarchies, programs can be speeded up by increasing their degree of locality. One human approach to locality optimization considers several small program instances of a given program, optimizes the instances for locality, and generalizes the structure of the solutions to the program. The paper suggests a semi-automatic locality-optimization method based on this approach. The major contribution is a local search algorithm that automatically optimizes program instances via combined code and data transformations. The algorithm uses a novel objective function that quantifies the intuitive notion of locality. Experimental results indicate that our method compares well with current compiler optimizations.