Temperature and electric field characteristics of time-dependentdielectric breakdown for silicon dioxide and reoxidized-nitrided oxides

TDDB characteristics of 150 Å reoxidized nitrided oxide (ONO) gate dielectrics were examined at temperatures from 77 K to 400 K. These ONO films were processed with different conditions of rapid thermal nitridation (RTN) and rapid thermal re-oxidation (RTO). Optimized ONO films show better Q_bd performance while maintaining a similar temperature and electric field dependence compared to SiO₂. The low temperature activation energy for ONO and SiO₂ is found to be strongly temperature dependent, and the charge to breakdown, Q_bd, is closely related to the electron trap generation/trapping rate rather than the amount of hole trapping for high field stress. To further verify the effect of hole trapping on TDDB, X-ray irradiation was applied to wafers at different process steps. The results clearly show that the amount of hole trapping does not correlate with the charge to breakdown     

Gate bias polarity dependence of charge trapping and time-dependentdielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm² for substrate injection, but less than 30 C/cm² for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q _BD in excess of 50 C/cm² is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

Effects of dynamic stressing on nitrided and reoxidized-nitridedchemical-vapor-deposited gate oxides

The degradation behaviour of thin (110 Å) nitrided and reoxidized-nitrided chemical-vapor-deposited (CVD) SiO₂ MOS gate dielectrics under dynamic voltage and current stressing is discussed. Results indicate that dynamic stressing increases charge-to-breakdown Q_bd and reduces charge trapping and midgap interface state generation within the dielectrics. These improvements, which can be explained by charge detrapping under dynamic stressing, depend on process conditions and the stress duty cycle     

Channel hot-carrier stressing of reoxidized nitrided silicondioxide

The mechanisms of channel hot-carrier-induced degradation in short n-channel MOSFETs with reoxidized nitrided oxide as the gate dielectric are discussed. Charge pumping measurements, supported by observations on the gate voltage dependence of degradation and the power law dependence of Δg_m on stress time, demonstrate that virtually no interface trap generation occurs in reoxidized nitrided oxides and that electron trapping is the dominant degradation mechanism. Although electron trapping can be enhanced in these dielectrics, this mechanism is not as important for device degradation as interface trap generation, and the net effect is substantially improved resistance to hot-carrier stress. A three-orders-of-magnitude improvement in device lifetime (versus conventional oxide) is demonstrated     

A new method for characterizing the spatial distributions ofinterface states and oxide-trapped charges in LDD n-MOSFETs

Previous studies showed that simultaneous determination of the interface states (Nit) and oxide-trapped charges (Q_ox) in the vicinity of the drain side in MOS devices was rather difficult. A new technique which allows a consistent characterization of the spatial distributions of both hot-carrier-induced Nit and Q_ox is presented. Submicron LDD n-MOS devices were tested and charge pumping measurements were performed. The spatial distributions of both Nit and Q _ox have been justified by two-dimensional (2-D) device simulation of the I-V characteristics for devices before and after the stress. Comparison of the drain current characteristics between simulation and experiment shows very good agreement. Moreover, results show that fixed-oxide charge effect is less pronounced to the device degradation for the experimental LDD-type n-MOS devices     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Role of electron traps in the radiation hardness of thermallynitrided silicon dioxide

A number of samples of thermally nitrided SiO₂ with varying concentrations of electron traps were studied in an attempt to correlate the radiation-induced oxide charge with the number of electron traps. Also studied were the detrapping characteristics of irradiated devices. Etch-back experiments were performed to locate the centroid of the trapped charge. The results show that electron trapping does play a role in the improved radiation hardness of nitrided SiO₂, but is not the sole cause of it     

Effect of rapid thermal reoxidation on the electrical properties ofrapid thermally nitrided thin-gate oxides

The authors report a systematic study of the impact of post-nitridation rapid thermal anneals in oxygen and nitrogen on the electrical properties of MOS devices with thin gate oxides. A comparative study of the two annealing ambients has led to the formulation of qualitative models to describe the charge trapping properties of the respective gate dielectrics. Roles of the post-nitridation anneals in altering the radiation and hot-electron sensitivity of the MOS devices are investigated and explained on the basis of structural changes in the gate oxides during nitridation and subsequent annealing. The performance and reliability of MOSFETs with reoxidized nitrided gate oxides are investigated. Overall, the results indicate that reoxidized nitrided oxides show improved charge trapping properties, better resistance to radiation and hot-carrier stress, and improved high-field electron mobility in MOSFETs     

Oxide thickness dependence of nitridation effects on TDDB characteristics

Wet oxide thicknesses dependence of nitridation effects on electrical characteristics, charge trapping properties and TDDB (Time Dependent Dielectric Breakdown) characteristics have been investigated. It is found that the difference of conduction current between the wet and nitrided wet oxide increases with increasing oxide thickness both for negative and positive bias to the gate until constant current stress is applied. After the stress, with decreasing oxide thickness both in wet and nitrided wet oxide leakage current increases. Up to 60 Å no difference was observed between the wet and nitrided wet oxide but at 50 Å nitrided wet oxide has less increase of current comparing to the wet oxide for the same stress. In wet oxide with increasing stress current density initial hole trap decreases but electron trap increases whereas in nitrided wet oxide has less initial hole trap and also electron trap is less comparing to the wet oxide. Both in wet and nitrided wet oxide for negative bias stress, time to 50 % breakdown decreases with decreasing thickness but at 50 Å a turn-around effect was observed due to nitridation i.e., the 50 % breakdown time is greater for nitrided wet oxide comparing to the wet oxide. On the contrary, for positive bias stress 50 % breakdown time increases with decreasing oxide thickness both in wet and nitrided wet oxide. For positive bias also a turn-around effect is observed at 50 Å i.e., 50% breakdown time is less in nitrided wet oxide comparing to the wet oxide. The improved reliability of nitrided wet oxide at the thin region of 50 Å seems to be due to the increase of more Si---N bond to the interface of oxide and Si comparing to the thick oxide of above 60 Å for the same nitridation conditions.     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

Effects of N distribution on charge trapping and TDDBcharacteristics of N2O annealed wet oxide

Wet pyrogenic oxide of different thicknesses was annealed in N₂O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 Å and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 Å, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N₂O annealed wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer t_BD was observed for N₂O annealed wet oxide of 51 Å compared to 98 Å. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N₂O ambient, the reliability of gate oxide will be improved in the ultrathin region     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of T_bd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of T_bd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.     

Effect of Nitrogen on the Frequency Dependence of Dynamic NBTI-Induced Threshold-Voltage Shift of the Ultrathin Oxynitride Gate P-MOSFET

The dynamic negative-bias-temperature-instability- induced threshold-voltage shift |DeltaV_t| of p-MOSFETs employing ultrathin decoupled-plasma- and thermal-nitrided SiO₂ gate dielectrics is studied as a function of gate frequency. The dependence of |DeltaV_t| on the gate frequency under unipolar stress is observed to become weaker for p-MOSFETs having higher nitrogen concentrations in the gate oxide. Evidence shows that reduced frequency dependence results from a greater lock-in of |DeltaV_t|, mainly due to an increased generation of recovery-resistant deep-level hole traps in the heavily nitrided gate p-MOSFET.     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

The generation and characterization of electron and hole trapscreated by hole injection during low gate voltage hot-carrier stressingof n-MOS transistors

Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V_g⩽V_d/4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, σ(1)≈3×10^-15 and σ(2)≈3×10^-16 cm²     

Kinetics of copper drift in PECVD dielectrics

We quantified the drift of Cu ions into various PECVD dielectrics by measuring shifts in capacitance-voltage behavior after subjecting Cu-gate MOS capacitors to bias-temperature stress. At a field of 1.0 MV/cm and temperature of 100°C, Cu ions drift readily into PECVD oxide with a projected accumulation of 2.7×10¹³ ions/cm ² after 10 years. However, in PECVD oxynitride, the projected accumulation under the same conditions is only 2.3×10¹⁰ ions/cm². These findings demonstrate the necessity of integrating drift barriers, such as PECVD oxynitride layers, in Cu interconnection systems to ensure threshold stability of parasitic field n-MOS devices