Ultra low-k die crack study for lead free solder bump flip-chip packaging

Ultra low-K (ULK) dielectric has lower mechanical strength (E < 8 GPa), lower cohesive strength and lower adhesion (<5 J/m²) than low-K and SiO₂ dielectric material. The packaging reliability test has shown that delamination between copper (Cu) and ULK is a major concern. In addition to the Cu and ULK delamination issue, the ULK die crack after temperature cycling test (TCT) showed die crack failure to be another issue. ULK die crack failure can be detected by C-mode scanning acoustic microscopy (CSAM). The CSAM image of the die crack mostly shows a crescent moon shape. The crack initiates at the upper edge of the underfill fillet penetrating the sidewall of the die, and then propagates toward the inside of the die. Finite element simulation indicates that the die crack failure starts at the backside edge of the die. The ULK die crack is caused by two mechanisms. First is the bending stress at the backside of the die, which is the result of the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. Second is the thermo-mechanical stress, which is the result of the local CTE mismatch between the silicon die and the underfill. The finite element simulation parametric study performed in this paper shows that a low underfill fillet height and a small fillet tip angle reduce the thermo-mechanical stress. In addition, attaching a heat sink to the surface of the flip-chip die increases packaging stiffness and resists the bending stress induced by the shrinkage of the substrate. Experimental results demonstrate that lowering the height of the underfill fillet, reducing the angle of the fillet tip and attaching a heat sink to the flip-chip die are effective ways to solve the ULK die crack issue.     

Thermal stress analysis and design optimization of direct chip attach (DCA) and chip scale package (CSP) in flip chip technology

Underfill encapsulation is a technique used to reinforce the solder bumps between the chip and the substrate in flip chip technology. To determine the optimal geometrical parameters and material properties for the package and candidate underfill materials is an important strategy for improving the thermo-mechanical reliability of flip chip packages. In this study, a stress-function-based energy method was developed to evaluate the interfacial peel and shear stress distributions in multilayered packaging structures. The stress functions were expressed in terms of sine and cosine trigonometric series. Simple programming and short CPU time lead to accurate stress distributions. After comparisons with other proposed numerical methods and results, the developed model was then coupled with a Genetic Algorithm to optimize the design of the direct chip attach (DCA) and chip scale package (CSP) in order to diminish the interfacial stresses and the possibility of crack initiation. The results revealed that the maximum peel and shear stress values were productively decreased and their peaks moved toward the center after conducting the optimizations in both cases. Improved geometrical and material parameters of the flip chip package were determined.     

Copper pillar bump design optimization for lead free flip-chip packaging

The interfacial delamination between the under bump metallurgy and the aluminum (Al) pad was observed in a copper (Cu) pillar bump evaluation in the work. The finite element analysis was employed to investigate the failure mechanism and the cu pillar bump geometry designed optimization. The finite element simulation result shows that the Cu pillar bump sustains the largest tensile stress at the temperature cycling test. The larger diameter Cu pillar bump can reduce the tensile stress significantly at the high temperature stress environment. Besides, an experiment confirms the finite element simulation result. Furthermore, an underfill with high glass transition temperature (T _g) and high modulus also improve the flip-chip ball grid array packaging reliability.     

底充胶及其材料模型对倒装焊热循环可靠性的影响

对倒装焊电子封装可靠性进行了热循环实验和有限元模拟,结果表明,有底充胶（underfill)时,SnPb焊点的热循环寿命可提高约16倍,并确定了Coffin-Manson半经验方程的参数,采用3种底充胶材料模型,亦即定常弹性模型,温度相关弹性模型和粘弹性材料模型,描述了底充胶U8347－3的力学性能。模拟结果表明,材料模型影响计算得到的SnPb焊点的塑性应范围,封装形变以及底充胶／芯片界面应力,采用弹性材料模型可能过高估计了SnPb焊点的热循环寿命和界面应力。     

Effect of underfill on bending fatigue behavior of chip scale package

This study evaluated the mechanical behavior of chip scale packages (CSPs) with the underfills using the four-point bending test. The bending fatigue durability in the CSP increased with increasing glass transition temperature (T _g ) of the underfill. The mechanical fatigue cracks occurred in the region between the (Ni,Cu)₃Sn₄ layer and the solder region near the upper substrate and the solder region of the CSP with the underfill which had the higher T _g . However, these cracks occurred in the region between the (Ni,Cu)₃Sn₄ layer and the Ni₃P layer near the bottom substrate and the solder region of the CSP with the underfill which had the lower T _g .     

Enhanced reliability of high-density wiring (HDW) substrates through new base substrate and dielectric materials

Flame retardant glass/epoxy composite (FR4) has been extensively used as a substrate material for microelectronic packaging due to its cost effectiveness and overall performance. However, to be able to fabricate high-density wiring with microvias, and embed capacitors, inductors, resistors, and RF and optoelectronic waveguides into a single substrate, we need materials other than FR4 as a base substrate to meet the stringent warpage requirements during fabrication. Typically, these base substrate materials should have a high modulus and good planarity in addition to having a coefficient of thermal expansion (CTE) that is close to that of silicon so that flip-chips can be attached directly to the substrate without the need for an underfill. Although low-CTE and high modulus base substrate materials can result in low warpage and can eliminate the need for an underfill, they can potentially cause delamination and cracking in the interlayer dielectric. This is due to the high CTE mismatch between the base substrate and a typical polymer dielectric. This paper aims to explore a combination of a base substrate material and an interlayer dielectric material such that the warpage is minimal, the dielectric will not crack or delaminate, and the flip-chip solder joints, assembled without an underfill, will not crack prematurely during qualification regimes or operating conditions. Non-linear finite element models with a design-of-simulations approach are used in arriving at optimized thermo-mechanical properties for the base substrate and the dielectric materials to enhance the overall reliability of the integrated substrate with flip-chip assembly. It is seen that an aluminum nitride base substrate with resin-coated foil C provides the best combination against dielectric cracking, high warpage, and solder joint fatigue. The results from the models have also been validated with experimental data.     

Evaluation of Residual Stress in Flip Chip Using 3-D Optical Interferometry/FEM Hybrid Technique

Abstract:  The residual stress in flip chips was investigated by a hybrid technique of 3-D finite element method (FEM) and 3-D optical interferometry. The residual stress consists of two parts: the chemical shrinkage stress caused by underfill curing and the thermal stress caused by coefficient of thermal expansion (CTE) mismatch and cooling. Warpage and in-plane deformation of the flip chip during the underfill curing and cooling procedure was real-time characterised with an integrated 3-D optical interferometry system. The measurement results were used to evaluate the chemical shrinkage stress and to verify/modify the FEM model for the analysis of thermal stress. It was found that the chemical shrinkage stress under isothermal curing condition is very small in average and negligible. As the difference between the simulated and measured thermal deformation falls within a limited scope, the accuracy of the simulated thermal stress can be guaranteed.     

Novel high performance no flow and reworkable underfills for flip-chip applications

 Flip-chip interconnect is the emerging technology for the high performance, high I/O (Inputs/Outputs) IC devices. Due to the thermal mismatch between the silicon IC (CTE=2.5 ppm/⁰ C) and the low cost organic substrate such as FR-4 printed wiring board (CTE=18–22 ppm/°C), the flip chip solder joints experience high shear stress during temperature cycling testing. Underfill encapsulant is used to couple the bilayer structure and is critical to the reliability of the flip-chip solder joint interconnects. Novel no-flow underfill encapsulant is an attractive flip-chip encapsulant due to the simplification of the no-flow underfilling process. To develop the no-flow underfill material suitable for the no-flow underfilling process of flip-chip solder joint interconnects, we have studied and developed a series of metal chelate latent catalysts for the no-flow underfill formulation. The latent catalyst has minimal reaction with the epoxy resin (cycloaliphatic type epoxy) and the crosslinker (or hardener) at the low temperature (<180° C) prior to the solder reflow and then rapid reaction takes place to form the low-cost high performance underfills. The effects of the concentration of the hardener and the catalyst on the curing profile and physical properties of the cured formulations were studied. The kinetics and exothermic heat of the curing reactions of these formulations were investigated by differential scanning calorimetry (DSC). Glass transition temperature (Tg) and coefficient of thermal expansion (CTE) of these cured resins were investigated by using thermo-mechanical analyzer (TMA). Storage moduli (G′) and crosslinking density of the cured formulations were measured by dynamic-mechanical analyzer (DMA). Weight loss of these formulations during curing was investigated by using thermo-gravimetric analyzer (TGA). Additionally, some comparison results of our successful novel generic underfills with the current commercial experimental no-flow underfills are reported. Additionally, approaches have been taken to develop the thermally reworkable underfill materials in order to address the non-reworkability problem of the commercial underfill encapsulants. These include introducing the termally cleavable blocks to thermoset resins, and adding additives to thermoset resins. For the first approach, five diepoxides containing thermally cleavable blocks were synthesized and characterized. These diepoxides were mixed with the hardener and the catalyst. Then the properties of these mixtures including Tg, onset decomposition temperature, storage modulus, CTE, and viscosity were studied and compared with those of the standard formulation based on the commercial epoxy: ERL-4221D. These mixtures all decompose at lower temperature than the standard formulation. Moreover, one mixture – Epoxy5 – showed acceptable Tg, low viscosity, and fairly good adhesion. For the latter approach, two additives were shown that after added to typical cycloaliphatic epoxy formulation, do not interfere with epoxy curing, and do not affect the typical properties of cured epoxy system, yet provide die removal capability to the epoxy. Furthermore, the combination of the two approaches showed positive results. Received: 28 September 1998 / Reviewed and accepted: 1 October 1998     

Analysis of fatigue delamination growth in flip-chip package

An incremental crack extension procedure is implemented for simulating the growth of an interface defect in an electronic flip-chip device subjected to fatigue temperature cycling. The distributions of fracture mechanics parameters including the strain energy release rate, the stress intensity factors and phase angles along the curvilinear front of an embedded corner defect on the interface of silicon die and underfill are estimated and substituted into a subcritical crack growth model to predict the evolution of the defect under cyclic loading condition. It is observed from the analysis that the corner defect is under crack faces contact condition during temperature cycling, and consequently, the delamination growth is under mode-II and mode-III driving forces. In addition, the crack growth rate is highest in the middle of the crack front, and the corner crack evolves from an initially concave front to a quarter-circular front under temperature cycling.     

Reliability of lead-free solder joints in CSP device under thermal cycling

Finite element method and Garofalo–Arrheninus creep model were combined and used to evaluate the reliability of different lead-free solder joints (SnAgCu, SnAg, SnSb and SnZn) and SnPb solder joints in chip scale package (CSP) 14 × 14 device under thermal cyclic loading. The results show that von Mises stress and equivalent creep strain in each of the four lead-free solder joints and SnPb solder joints were strongly different, increasing in the order SnPb < SnAg < SnSb < SnZn < SnAgCu. It is found that maximum stress–strain concentrates on the top-surface of corner solder joints in the CSP device for all solder joints, and SnAgCu solder joints shows the highest fatigue life among those five kinds of solder joints.     

高温下不同银含量微电子胶连点的力学性能及膨胀系数不匹配热应力

采用热机械分析仪和微压入测试系统对不同银含量微电子互连导电胶进行测试表征,并基于数值模拟分析其用于倒装芯片封装时胶层的不匹配热应力。结果表明,较高银含量固化导电胶的玻璃化转变温度滞后于较低银含量固化导电胶,且其热膨胀系数较低;随着温度的升高,导电胶的模量与硬度由玻璃态时的较高值降低到高弹态时的较低水平,且银含量较高时的刚度与强度较大;各不匹配热应力分量随温度的变化呈现出"蝌蚪状"或"半蝌蚪状",玻璃态时用于倒装芯片封装的导电胶未发生屈服。     

On the Through-the-Width Multiple Delamination, and Buckling and Postbuckling Behaviors of Symmetric and Unsymmetric Composite Laminates

Multiple delamination causes severe degradation of the stiffness and strength of composites. Interactions between multiple delamination, and buckling and postbuckling under compressive loads add the complexity of mechanical properties of composites. In this paper, the buckling, postbuckling and through-the-width multiple delamination of symmetric and unsymmetric composite laminates are studied using 3D FEA, and the virtual crack closure technique with two delamination failure criteria: B-K law and power law is used to predict the delamination growth and to calculate the mixed-mode energy release rate. The compressive load-strain curves, load-central deflection curves and multiple delamination process for eight composite specimens with different initial delamination sizes and their distributions as well as two angle-ply configurations 0₄//(±θ)₆//0₄ (θ?=?0° and 45°, and “//” denotes the delaminated interface) are comparatively studied. From numerical results, the unsymmetry decreases the local buckling load and initial delamination load, but does not affect the global buckling load compared with the symmetric laminates. Besides, the unsymmetry affects the unstable delamination and buckling behaviors of composite laminates largely when the initial multiple delamination sizes are relatively small.     

残余应力对压头诱导的硬质薄膜/韧性基底材料体系界面分层机制的影响

硬质薄膜在工程应用中经常承受高载荷作用。在接触载荷下,薄膜/基底体系通常产生剪切分层破坏和法向分层破坏,并直接影响材料的可靠性。硬质薄膜中较大的残余应力对界面分层破坏影响不容忽视。该文基于内聚力模型,采用有限元方法模拟残余应力对压头诱导的硬质薄膜/韧性基底界面分层破坏的影响规律;给出在不同残余应力下薄膜/基底界面分层破坏时的临界压入深度以及临界载荷;获得考虑残余应力时硬质薄膜/韧性基底界面分层破坏失效图,进而对薄膜材料的工程应用和采用压痕法测量界面结合性能提供指导。     

Analysis of stress intensity factors for three-dimensional interface crack problems in electronic packages using the virtual crack closure technique

In this study the fracture mechanics parameters, including the strain energy release rate, the stress intensity factors and phase angles, along the curvilinear front of a three-dimensional bimaterial interface crack in electronic packages are considered by using finite element method with the virtual crack closure technique (VCCT). In the numerical procedure normalized complex stress intensity factors and the corresponding phase angles (Rice, J Appl Mech 55:98–103, 1988) are calculated from the crack closure integrals for an opening interface crack tip. Alternative procedures are also described for the cases of crack under inner pressure and crack faces under large-scale contact. Validation for the procedure is performed by comparing numerical results to analytical solutions for the problems of interface crack subjected to either remote tension or mixed loading. The numerical approach is then applied to study interface crack problems in electronic packages. Solutions for semi-circular surface crack and quarter-circular corner crack on the interface of epoxy molding compound and silicon die under uniform temperature excursion are presented. In addition, embedded corner delaminations on the interface of silicon die and underfill in flip-chip package under thermomechanical load are investigated. Based on the distribution of the fracture mechanics parameters along the interface crack front, qualitative predictions on the propensity of interface crack propagation under thermomechanical loads are given.     

Failure analysis of large press die holder

This paper studied the cracking mode and mechanism of the large press die holder. Detailed investigations including macroscopic examination, metallographic observation, microfractography, chemical analysis and mechanical properties analysis were carried out. The investigations reveal that the failure mechanism of the die holder is fast brittle fracture caused by high stress under the condition of material embrittlement. The main crack originated from the fillet of the die holder. The serious impact toughness degeneration at the bottom of the die holder resulted in the material embrittlement. The transmission electron microscopy (TEM) investigation indicates that the material properties degeneration is related to the coarsening precipitates of M₂₃C₆ and M₆C. The finite element analysis (FEA) demonstrates that the fillet suffering high stress is the weak part of the die holder.     

Tensile-force-induced delamination of polymeric coatings in tightly jacketed double-coated optical fibers

To maintain the mechanical strength, the glass fiber of optical fibers is coated by polymeric materials during the fabrication process. However, when the external tensile-force-induced shear stress at the interface of the glass fiber and primary coating is larger than its adhesive stress, the polymeric coatings will be delaminated from the glass fiber and optical fiber will lose its mechanical strength. In this article, the tensile-force-induced delamination of polymeric coatings in tightly jacketed double-coated optical fibers is investigated. To minimize the coating's delamination, the tensile-force-induced shear stress at the interface of the glass fiber and primary coating should be reduced. The method to minimize such a shear stress is to select suitable polymeric coatings as follows. The Poisson's ratio of the primary coating and the Young's moduli of the secondary coating and jacket should be increased, but the Young's modulus of the primary coating and thickness of the secondary coating should be decreased. On the other hand, the thickness of the primary coating has an optimal value. The selection of the adhesive shear stress between the glass fiber and primary coating in the minimization of the coating's delamination is also discussed.     

高硼硅玻璃沙拉碗缓冲包装跌落仿真分析

目的 研究高硼硅玻璃沙拉碗跌落冲击时的应力和变形情况,为沙拉碗安全包装提供参考。方法 运用Pro/E软件和Ansys软件建立沙拉碗及其缓冲包装三维有限元模型,对有无缓冲包装以及不同跌落高度和跌落姿态分别进行跌落仿真模拟,获取沙拉碗跌落冲击过程的应力、变形和加速度分布及变化规律。结果 沙拉碗跌落冲击时,最易损坏的部位在上部边缘、底部缓冲包装棱边及角的冲击部位;无缓冲包装时最大应力和脆值分别为76 MPa和1.84×105g,有缓冲包装时的最大应力和脆值分别为0.139 MPa和73.5g。结论 对沙拉碗进行包装设计时,应加强对上部碗口边缘部位和缓冲垫边角的保护;缓冲包装结构对沙拉碗起到了明显的保护作用,该研究为高硼硅沙拉碗缓冲包装的理论研究和结构优化设计提供了参考。     

Surface and buried interfacial structures of epoxy resins used as underfills studied by sum frequency generation vibrational spectroscopy

Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.     

Exploring water and ion transport process at silicone/copper interfaces using in-situ electrochemical and Kelvin probe approaches

In general,packaging materials which encapsulate light emitting diodes(LEDs)and microelectronic devices offer barrier protection against several environmental hazards such as water and ionic contaminants.However,these encapsulants may provide pathways for water and ionic contaminants to reach the metal/polymer interfaces and provoke local corrosion of electronics,which is a major reliability concern for polymer encapsulated LEDs and microelectronics.As the water and corrosive constituents play a crucial role in their reliability,water uptake kinetics,interfacial ion transport and delamination behaviour of silicone coated copper model system,mimicking a typical microelectronics packaging system,is explored in the present work.Electrochemical impedance spectroscopy(EIS)integrated with attenuated total reflection Fourier transform infrared(ATR-FTIR)spectroscopy studies revealed that water diffusion inside the silicone network is Fickian in nature and the evolution of the observed time constants are related to the diffusion and interfacial reactions.A decrease of impedance magnitude with time was observed in EIS measurements concurrently with water absorption bands shifting towards lower wavenumber in ATR-FTIR measurements,implying the growth of strong hydrogen bonding between water molecules and the silicone network.The estimated diffusion constant of water using the capacitance method was in the order of 7×10^-12m²s^-1and the water absorption volume fraction was in the range of 0%to 0.30%.Scanning Kelvin probe studies elucidated the ion transport process occurring at the silicone/copper interface in a humid atmosphere.The interfacial ion transport process is controlled by the interfacial electrochemical reactions at the cathodic delamination front and the estimated average delamination rate is 0.43 mm h^-1/2.This work demonstrates that exploring ion and water transport in the silicone coating and along the silicone/copper interface is of pivotal importance as part of a detailed reliability assessment of the polymer encapsulated LEDs and microelectronics.     

Experimental study on delamination migration in composite laminates

The transition of delamination growth between different ply interfaces in composite tape laminates, known as migration, was investigated experimentally. The test method used promotes delamination growth initially along a 0/θ ply interface, which eventually migrates to a neighbouring θ/0 ply interface. Specimens with θ = 60° and 75° were tested. Migration occurs in two main stages: (1) the initial 0/θ interface delamination turns, transforming into intraply cracks that grow through the θ plies; this process occurs at multiple locations across the width of a specimen, (2) one or more of these cracks growing through the θ plies reaches and turns into the θ/0 ply interface, where it continues to grow as a delamination. A correlation was established between these experimental observations and the shear stress sign at the delamination front, obtained by finite element analyses.Overall, the experiments provide insight into the key mechanisms that govern delamination growth and migration.