硼原子对Si(100)衬底上Ge量子点生长的影响

研究了硼原子对Si(100)衬底上Ge量子点自组织生长的影响.硼原子的数量由0单原子层变到0.3单原子层.原子力显微镜的观察表明,硼原子不仅对量子点的大小,而且对其尺寸均匀性及密度都有很大影响.当硼原子的数量为0.2单原子层时,获得了底部直径为60±5nm,面密度为6×109cm-2,且均匀性很好的Ge量子点.另外,还简单讨论了硼原子对Ge量子点自组织生长影响的机制.     

硼原子对Si(100)衬底上Ge量子点生长的影响

研究了硼原子对 Si( 1 0 0 )衬底上 Ge量子点自组织生长的影响 .硼原子的数量由 0单原子层变到 0 .3单原子层 .原子力显微镜的观察表明 ,硼原子不仅对量子点的大小 ,而且对其尺寸均匀性及密度都有很大影响 .当硼原子的数量为 0 .2单原子层时 ,获得了底部直径为 60± 5nm,面密度为 6× 1 0 9cm- 2 ,且均匀性很好的 Ge量子点 .另外 ,还简单讨论了硼原子对 Ge量子点自组织生长影响的机制 .     

多层Ge量子点的生长及其光学特性

用超高真空化学气相淀积系统在Si(100)衬底上生长了多层Ge量子点.分别用TEM和AFM分析了埋层和最上层量子点的形貌和尺寸,研究了量子点层数和Si隔离层厚度对上层Ge量子点的形状和尺寸分布的影响.观察到样品的低温PL谱线有明显蓝移(87meV),Ge量子点的PL谱线的半高宽度(FWHM)为46meV,说明采用UHV/CVD生长的多层量子点适合量子光电器件的应用.     

多层Ge量子点的生长及其光学特性

用超高真空化学气相淀积系统在Si(1 0 0 )衬底上生长了多层Ge量子点.分别用TEM和AFM分析了埋层和最上层量子点的形貌和尺寸,研究了量子点层数和Si隔离层厚度对上层Ge量子点的形状和尺寸分布的影响.观察到样品的低温PL谱线有明显蓝移(87meV) ,Ge量子点的PL谱线的半高宽度(FWHM )为46meV ,说明采用UHV/CVD生长的多层量子点适合量子光电器件的应用     

磁控溅射Ge/Si多层膜的发光特性研究

采用磁控溅射技术,在Si(100)衬底上制备了一系列不同周期、不同Ge层厚度的Ge/Si多层膜样品.用室温光致发光(PL)、Raman散射和AFM图谱对样品进行表征.结果表明:Ge/Si多层膜中的PL发光峰主要来自于Ge晶粒,并且Ge晶粒生长的均匀性对PL发光影响较大,生长均匀的Ge晶粒中量子限域效应明显,随着晶粒的减小,PL发光主峰发生蓝移;在Ge晶粒均匀性较差时,PL发光峰强度较弱,量子限域效应不明显.     

Si(001)斜切衬底上Ge量子点的固相外延生长

研究了Si(001)面偏[110]方向6°斜切衬底上Ge量子点的固相外延生长.实验结果表明,在Si(001)6°斜切衬底上固相外延生长Ge量子点的最佳退火温度为640℃,在斜切衬底上成岛生长的临界厚度低于在Si(001)衬底成岛生长的临界厚度,6°斜切衬底上淀积0.7nm Ge即可成岛,少于Si(001)衬底片上Ge成岛所需的淀积量.从Ge量子点的密度随固相外延温度的变化曲线,得到Ge量子点的激活能为1.9eV,远高于Si(111)面上固相外延Ge量子点的激活能0.3eV.实验亦发现,在Si(001)斜切衬底上固相外延生长的Ge量子点较Si(001)衬底上形成的量子点的热稳定性要好.     

Si(001)斜切衬底上Ge量子点的固相外延生长

研究了Si(001)面偏[110]方向6°斜切衬底上Ge量子点的固相外延生长.实验结果表明,在Si(001)6°斜切衬底上固相外延生长Ge量子点的最佳退火温度为640℃,在斜切衬底上成岛生长的临界厚度低于在Si(001)衬底成岛生长的临界厚度,6°斜切衬底上淀积0.7nm Ge即可成岛,少于Si(001)衬底片上Ge成岛所需的淀积量.从Ge量子点的密度随固相外延温度的变化曲线,得到Ge量子点的激活能为1.9eV,远高于Si(111)面上固相外延Ge量子点的激活能0.3eV.实验亦发现,在Si(001)斜切衬底上固相外延生长的Ge量子点较Si(001)衬底上形成的量子点的热稳定性要好.     

弛豫SiGe衬底上SiGe/SiⅡ型量子阱

采用 UHV / CVD系统 ,在 Si衬底上生长了具有渐变 Si1 - x Gex 缓冲层结构的弛豫 Si0 .76 Ge0 .2 4虚衬底和 5个周期的 Si0 .76 Ge0 .2 4/ Si多量子阱 .在渐变 Si1 - x Gex 缓冲层生长过程中引入原位退火 ,消除了残余应力 ,抑制了后续生长的 Si Ge中的位错成核 .透射电子显微照片显示 ,位错被有效地限制在组份渐变缓冲层内 ,而 Si Ge上层和 Si Ge/Si量子阱是无位错的 .在样品的 PL 谱中 ,观察到跃迁能量为 0 .96 1e V的 型量子阱的无声子参与 (NP)发光峰 .由于 型量子阱中电子和空穴不在空间同一位置 ,较高光功率激发下引起的高浓度载流子导致能带弯     

量子点的形成对Si/Ge界面互扩散的影响

在Si(100)衬底上低温生长了一层完全应变的Ge层,高温退火形成量子点.我们用喇曼光谱研究了量子点形成时Si/Ge界面的互扩散现象,实验表明量子点的形成伴随着Si/Ge原子之间的互扩散,通常在Si衬底上形成的是SiGe合金量子点,而不是纯Ge量子点.     

量子点的形成对Si/Ge界面互扩散的影响

在Si(100)衬底上低温生长了一层完全应变的Ge层,高温退火形成量子点.我们用喇曼光谱研究了量子点形成时Si/Ge界面的互扩散现象,实验表明量子点的形成伴随着Si/Ge原子之间的互扩散,通常在Si衬底上形成的是SiGe合金量子点,而不是纯Ge量子点.     

Photoluminescence line width of self-assembled Ge(Si) islands arranged between strained Si layers

The effect of variations in the strained Si layer thicknesses, measurement temperature, and optical excitation power on the width of the photoluminescence line produced by self-assembled Ge(Si) nanoislands, which are grown on relaxed SiGe/Si(001) buffer layers and arranged between strained Si layers, is studied. It is shown that the width of the photoluminescence line related to the Ge(Si) islands can be decreased or increased by varying the thickness of strained Si layers lying above and under the islands. A decrease in the width of the photoluminescence line of the Ge(Si) islands to widths comparable with the width of the photoluminescence line of quantum dot (QD) structures based on direct-gap InAs/GaAs semiconductors is attained with consideration of diffusive smearing of the strained Si layer lying above the islands.     

Transition from the two- to three-dimensional growth of Ge films upon deposition onto relaxed SiGe/Si(001) buffer layers

The critical thickness of the two-dimensional growth of Ge on relaxed SiGe/Si(001) buffer layers different in Ge content is studied in relation to the parameters of the layers. It is shown that the critical thickness of the two-dimensional growth of Ge on SiGe buffer layers depends on the lattice mismatch between the film and the substrate and, in addition, is heavily influenced by Ge segregation during SiGe-layer growth and by variations in the growth-surface roughness upon the deposition of strained (stretched) Si layers. It is found that the critical thickness of the two-dimensional growth of Ge directly onto SiGe buffer layers with a Ge content of x = 11–36% is smaller than that in the case of deposition onto a Si (001) substrate. The experimentally detected increase in the critical thickness of the two-dimensional growth of Ge with increasing thickness of the strained (stretched) Si layer predeposited onto the buffer layer is attributed to a decrease in the growth-surface roughness and in the amount of Ge located on the surface as a result of segregation.     

Light-emitting tunneling nanostructures based on quantum dots in a Si and GaAs matrix

InGaAs/GaAs and Ge/Si light-emitting heterostructures with active regions consisting of a system of different-size nanoobjects, i.e., quantum dot layers, quantum wells, and a tunneling barrier are studied. The exchange of carriers preceding their radiative recombination is considered in the context of the tunneling interaction of nanoobjects. For the quantum well-InGaAs quantum dot layer system, an exciton tunneling mechanism is established. In such structures with a barrier thinner than 6 nm, anomalously fast carrier (exciton) transfer from the quantum well is observed. The role of the above-barrier resonance of states, which provides “instantaneous” injection into quantum dots, is considered. In Ge/Si structures, Ge quantum dots with heights comparable to the Ge/Si interface broadening are fabricated. The strong luminescence at a wavelength of 1.55 μm in such structures is explained not only by the high island-array density. The model is based on (i) an increase in the exciton oscillator strength due to the tunnel penetration of electrons into the quantum dot core at low temperatures (T < 60 K) and (ii) a redistribution of electronic states in the Δ₂-Δ₄ subbands as the temperature is increased to room temperature. Light-emitting diodes are fabricated based on both types of studied structures. Configuration versions of the active region are tested. It is shown that selective pumping of the injector and the tunnel transfer of “cold” carriers (excitons) are more efficient than their direct trapping by the nanoemitter.     

Ge/Si Self-Assembled Quantum Dots and Their Optoelectronic Device Applications

In recent years, quantum dots have been successfully grown by self-assembling processes. For optoelectronic device applications, the quantum-dot structures have advantages such as reduced phonon scattering, longer carrier lifetime, and lower detector noise due to low-dimensional confinement effect. Comparing to traditional optoelectronic III-V and other materials, self-assembled Ge quantum dots grown on Si substrates have a potential to be monolithically integrated with advanced Si-based technology. In this paper, we describe the growth of self-assembled, guided Ge quantum dots, and Ge quantum-dot superlattices on Si. For dot growth, issues such as growth conditions and their effects on the dot morphology are reviewed. Then vertical correlation and dot morphology evolution are addressed in relation to the critical thickness of Ge quantum-dot superlattices. In addition, we also discuss the quantum-dot p-i-p photodetectors (QDIPs) and n-i-n photodetectors for mid-infrared applications, and the quantum-dot p-i-n photodetectors for 1.3-1.55 mum for communications applications. The wavelength of SiGe p-i-p QDIP can be tuned by the size as grown by various patterning methods. Photoresponse is demonstrated for an n-i-n structure in both the mid-infrared and far-infrared wavelength ranges. The p-i-n diodes exhibit low dark current and high quantum efficiency. The characteristics of fabricated light-emitting diode (LED) devices are also discussed, and room-temperature electroluminescence is observed for Ge quantum-dot LED. The results indicate that Ge dot materials are potentially applicable for mid-infrared (8-12 mum) detectors as well as fiber-optic (1.3-1.55 mum) communications.     

Self-assembling Ge(Si)/Si(100) quantum dots

The morphological evolution of self-assembled epitaxial quantum dots on Si(100) is reviewed. This intensely investigated material system continues to provide fundamental insight guiding the growth of nanostructured electronic materials. Self-assembled quantum dots are faceted, three-dimensional islands which grow atop a planar wetting layer. Pure Ge growth at higher substrate temperatures results in narrower island size distributions but activates additional strain-relief mechanisms which will alter the optical and electronic properties of the dots. Optical and electrical characterization has shown that electrons and holes are confined to different regions of the dot. This results in a spatially indirect, type II recombination mechanism. Emerging device applications which exploit properties of these nanoscale Ge islands are discussed.     

Photoinduced and equilibrium optical absorption in Ge/Si quantum dots

The results of studies of the optical absorption spectra in Ge/Si quantum dot structures in the mid-infrared region are reported. Two types of structures different in terms of the method used for quantum dot formation and in terms of barrier layer thickness are explored. The photoinduced absorption associated with the nonequilibrium population of hole states and optical absorption in structures doped to different levels are investigated. Specific features that are associated with occupation of the ground and excited states of quantum dots and exhibit a polarization dependence are observed. From the experimental data, the energy spectrum of holes is determined for structures of both types.     

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiO _x -cladded Si or GeO _x -cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO₂. Simulations involving self-consistent solutions of the Poisson and Schrödinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.