Laser-recrystallized silicon thin-film transistors on expansion-matched 800°C glass

Laser-recrystallized silicon thin-film transistors (TFT's) have been fabricated, for the first time, on a novel, potentially low-cost glass substrate, The 0.5-µm-thick silicon films were deposited along with appropiate dielectric layers on Corning Code 1729 glass substrates and recrystallized using an argon ion laser. The n-channel enhancement-mode transistors were made using conventional IC device fabrication procedures modified to have a maximum processing temperature of 800°C. Transistor's made in the recrystallized silicon show field-effect electron mobilities as high as 270 cm²/V.s, approximately 15 times that of comparable devices made in as-deposited polycrystalline-silicon films. The recrystallized silicon devices also exhibit lower threshold voltages and lower leakage currents than do comparable polycrystalline-silicon devices.     

Polycrystalline silicon thin-film transistors with two-stepannealing process

Thin-film transistors (TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature furnace annealing and high-temperature rapid thermal annealing leads to a significant improvement in the material quality. The TFTs obtained with this two-step annealing material exhibit better measured characteristics than those obtained by using conventional furnace annealing     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Polycrystalline silicon films and thin-film transistors using solution-based metal-induced crystallization

Polycrystalline silicon (poly-Si) films consisting of dish-like and wadding-like domains were obtained with solution-based metal-induced crystallization (SMIC) of amorphous silicon. The Hall mobility of poly-Si was much higher in dish-like domains than in wadding-like domains. Thin-film transistors (TFTs) have been prepared using those two kinds of poly-Si films as the active layer, followed by the phosphosilicate glass (PSG) nickel gettering. The field effect mobility of dish-like domain poly-Si TFTs and wadding-like poly-Si TFTs were 70/spl sim/80 cm/sup 2//V/spl middot/s and 40/spl sim/50 cm/sup 2//V/spl middot/s, respectively. With a multi-gate structure, the leakage current of poly-Si TFTs was reduced by 1 to 2 orders of magnitude. In addition, the gate-induced drain leakage current (GIDL) and uniformity of the drain current distribution were also improved. P-type TFTs fabricated using SMIC exhibited excellent reliability.     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Amorphous silicon thin-film transistors on steel foil substrates

We report the successful fabrication of high-quality a-Si:H thin-film transistors (TFTs) on stainless steel foil substrates. TFTs with an inverted-staggered structure were grown on 200-μm thick stainless steel foil. These TFTs show typical ON/OFF current ratios of 10⁷, OFF currents on the order of 10^-12 A, good linear and saturation current behavior, subthreshold slopes of 0.5 V/decade, and linear channel mobilities of 0.5 cm²/V. In addition, we have demonstrated that these TFTs are capable of withstanding significant mechanical shocks, as well as macroscopic deformation of the substrate, while remaining functional. This work demonstrates that transistor circuits can be made on a flexible, nonbreakable substrate. Such circuits would be highly useful in reflective or emissive displays, and in other applications that require rugged macroelectronic circuits     

Amorphous silicon thin-film transistors on compliant polyimide foilsubstrates

Much of the mechanical strain in semiconductor devices can be relieved when they are made on compliant substrates. We demonstrate this strain relief with amorphous silicon thin-film transistors made on 25-μm thick polyimide foil, which can be bent to radii of curvature R down to 0.5 mm without substantial change in electrical characteristics     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Amorphous silicon phototransistor on a glass substrate

An amorphous silicon n⁺-i-p⁺-i-n⁺thin-film phototransistor was made on a glass substrate. The p⁺base is very thin (∼ 200 Å) compared with 2000 to 5000 Å of the collector i-layer. Therefore, the emitter current which is induced from the photogenerated flux in the collector i-layer is very high. In addition, hole lifetime (minority carrier in the emitter) and transit time are very short, the device possesses fast rise time and fall time of 30 µs, which is mainly governed by the junction capacitance-resistance charging effect and strays.     

Effects of gamma-ray irradiation on polycrystalline silicon thin-film transistors

The effects of gamma-ray irradiation on the performance of polycrystalline silicon thin-film transistors are investigated. After irradiation, the threshold voltage of the TFTs is shifted negatively and well-defined kinks are formed in the subthreshold regions of the transfer characteristics, explained by the turn-on of back channel and sidewall leakage current paths. In the non-irradiated device, the leakage current I_L is controlled by the reverse biased drain junction, while after irradiation I_L is limited by the intrinsic resistance of the polysilicon material itself.     

Polycrystalline silicon thin films on glass by aluminum-inducedcrystallization

This work focuses on the development and characterization of device quality thin-film crystalline silicon layers directly onto low-temperature glass. The material requirements and crystallographic quality necessary for high-performance device fabrication are studied and discussed. The processing technique investigated is aluminum-induced crystallization (AIC) of sputtered amorphous silicon on Al-coated glass substrates. Electron and ion beam microscopy are employed to study the crystallization process and the structure of the continuous polycrystalline silicon layer. The formation of this layer is accompanied by the juxtaposed layers of Al and Si films exchanging places during annealing. The grain sizes of the poly-Si material are many times larger than the film's thickness. Raman and thin-film X-ray diffraction measurements verify the good crystalline quality of the Si layers. The electrical properties are investigated by temperature dependent Hall effect measurements. They show that the electrical transport is governed by the properties within the crystallites rather than the grain boundaries. The specific advantages of AIC are: (1) its simplicity and industrial relevance, particularly for the processes of sputter deposition and thermal evaporation, (2) it requires only low-temperature processing at 500°C, (3) its short processing times, and (4) its ability to produce polycrystalline material with good crystallographic and electrical properties. These advantages make the poly-Si material formed by AIC highly interesting and suitable for subsequent device fabrication such as for poly-Si thin-film solar cells     

Inverter circuits on glass substrates based on ZnO-nanoparticle thin-film transistors

The integration technique and the properties of inverter circuits on glass substrates using ZnO nanoparticles as semiconductor material are presented. The inverter device consists of a switching and a load metal–insulator–semiconductor field-effect transistor with poly(4-vinylphenol) as the gate dielectric. Although the semiconductor is deposited by spin-coating of a colloidal ZnO dispersion and the process temperature is limited to 200 °C, the inverters show reasonable maximum peak gains at low power consumption. The maximum peak gain was 6 V/V, whereas the maximum static power dissipation density was less than 26 nW/μm². Additionally, the influence of the geometry ratio as well as of the supply voltage on the device performance has been investigated. With regard to the optical characteristics, the proposed technique leads to circuits with an optical transmittance of up to 80%.     

The performance of X-band Gunn oscillators over the temperature range 30°C to 120°C

The output power of a cavity-controlled Gunn oscillator has been measured at a frequency of 10 GHz, as a function of bias voltage over the temperature range 30°C to 120°C. The measurements were made using 500-ns pulses to avoid significant changes in-device temperature during a pulse, and at a duty cycle of 20:1 to maintain a low mean input power. The device was operated in a coaxial cavity made of invar, and temperature control effected by operating the cavity in an oven. It has been found that ranges of bias voltages exist over which power output and efficiency is extremely sensitive to temperature changes, and that, depending on the particular conditions, power output can either increase or decrease. The effect of increasing temperature has also been found to reduce the bias voltage required to obtain maximum power output and efficiency.     

Bipolar transistor fabrication in low-temperature (745°C) ultra-low-pressure chemical-vapor-deposited epitaxial silicon

In this letter we report for the first time the successful fabrication of bipolar transistors in low-temperature (Tdep= 745°C) epitaxial silicon deposited by a chemical-vapor-deposition (CVD) technology. The epitaxial layers were deposited by an ultra-low-pressure CVD (U-LPCVD) technique utilizing an optimized in-situ predeposition argon sputter clean. The critical parameter during the sputter clean has been identified as the substrate bias. Bias voltages of -200 or -300 V create dislocations that form emitter-collector shunts during the bipolar transistor fabrication process; a bias voltage of -100 V, however, permits the deposition of essentially defect-free (<10 dislocations cm^-2by defect etching) epitaxial films suitable for bipolar transistor fabrication.     

Electrophotographic patterning of thin-film silicon on glass foil

We report the patterning of thin films of amorphous silicon (a-Si:H) using electrophotographically applied toner as the etch mask. Using a conventional xerographic copier, a toner pattern was applied to 0.1 μm thick a-Si:H films deposited on ~50 μm thick glass foil. The toner then served as the etch mask for a-Si:H, and as the lift-off material for the patterning of chromium. This technique opens the prospect of roll-to-roll, high-throughput patterning of large-area thin-film circuits on glass substrates     

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.     

Dimensional effects on the reliability of polycrystalline silicon thin-film transistors

We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I_min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated Si-H bonds.     

Fabrication and characterization of bipolar transistors within-situ doped low-temperature (800°C) epitaxial silicon

The authors report the fabrication of bipolar transistors at a maximum process temperature of 800°C, utilizing in situ doped low-temperature epitaxial silicon deposited by ultralow-pressure chemical vapor deposition (U-LPCVD), and their subsequent characterization. The epitaxial silicon layers form the collector, base, and emitter layers. To attain a high donor concentration in the epitaxial emitter layer, the U-LPCVD process is plasma enhanced. Transistors having excellent DC characteristics down to collector currents of ~10 pA/μm² are obtained, which indicates that the bulk quality of the epitaxial films is good enough for device fabrication     

Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

Single-crystalline silicon thin film on glass (cSOG) has been prepared using an "ion-cutting" based "layer-transfer" technique. Low-temperature processed thin-film transistors, fabricated both on cSOG and metal-induced laterally crystallized polycrystalline silicon, have been characterized and compared. The cSOG-based transistors performed comparatively better, exhibiting a significantly higher electron field-effect mobility (/spl sim/430 cm/sup 2//Vs), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias.     

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO2) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO2laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm²/V sec and leakage currents < 10 pA, for a Channel length of 12 µm and width of 20 µm. Achievement of high-performance TFT's with the combined features of microcrack suppression, preferred orientation, and selected-area crystallization render CO2- laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.