Program schemes for multilevel flash memories

This paper presents a synthetic overview of multilevel (ML) flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler-Nordheim tunneling (FNT) are discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absorption, with positive effects on the degree of parallelism and program throughput. As for FNT, much faster programming than that commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability.     

A novel algorithm for high-throughput programming of multilevel flash memories

This paper presents a new method to program multilevel (ML) flash memories that combines ramped-gate programming with minimum verification of the sense transistor threshold voltage, in order to achieve high program throughput, i.e., number of bits programmed per second. Such a method is studied by means of extensive measurements on production quality test chips and is found able to allow a program throughput about three times as large as the state of the art presented in the literature. Furthermore, it is found adequate for 3-bit-per-cell multilevel schemes, while for the extension to the 4-bit-per-cell case the use of error correcting codes cannot be avoided.     

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-μm flash memory process and successfully operated at a low voltage of 1.5 V     

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories

Constant-charge-injection programming (CCIP) has been proposed as a way to achieve high-speed multilevel programming in flash memories. In order to achieve high programming throughput in multilevel flash memory, programming method must provide: 1) high-speed cell-programming; 2) high programming efficiency; and 3) highly uniform programming characteristics. Conventional source-side channel-hot-electron injection (SSI) programming realizes both fast cell-programming and high programming efficiency, but the large cell-to-cell variation in programming speed with SSI is a problem. CCIP reduces the characteristic variation of SSI programming and satisfies all of the above requirements. By applying CCIP to 2-bit/cell AG-AND flash memory, the high programming throughput of 10.3 MB/s is obtained with no area penalty. This is 1.8 times faster than the throughput with conventional SSI programming.     

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

In order to scale high-voltage transistors for high-density negative-gate channel-erasing NOR flash memories, two circuit techniques were developed. A proposed level shifter with low operating voltage is composed of three parts, a latch holding the negative erasing voltage, two coupling capacitors connected with the latched nodes in the latch, and high-voltage drivers inverting the latch, resulting in reduction of the maximum internal voltage by 0.5 V. A proposed high-voltage generator adds a path-gate logic to a conventional high-voltage generator to realize both low noise and low ripple voltage, resulting in a reduction of the maximum internal voltage by 0.5 V. As a result, these circuit techniques along with high coupling-ratio cell technology can scale down the high-voltage transistors by 15% and can realize higher density negative-gate channel-erase NOR flash memories in comparison with the source-erase NOR flash memories.     

FTL algorithms for NAND-type flash memories

Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated via the time consuming erase operation. Furthermore, every block in flash memory has a limited program/erase cycle. In order to manage these issues, the flash memory controller can be integrated with a software module called the flash translation layer (FTL). This paper surveys the state-of-art FTL algorithms. The FTL algorithms can be classified by the complexity of the algorithms: basic and advance. Furthermore, they can be classified by their corresponding tasks: performance enhancement and durability enhancement. The FTL algorithms corresponding to each classification are further broken down into various schemes depending on the methods they adopt. This paper also provides the information of hardware features of flash memory for FTL programmers.     

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated     

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.     

Program load adaptive voltage generator for flash memories

This paper describes a program load voltage generator for flash memories. It is based on an adaptive feedback loop which senses the current delivered to the memory cells during programming and adjusts the output voltage accordingly to compensate for the voltage drop caused by the programming current across the bit-line select transistors. The proposed circuit (silicon area=0.065 mm²) was integrated in a 0.8-μm CMOS 4 Mb flash memory device (0.6 μm in the matrix). Experimental evaluations showed that very effective compensation is achieved, with bit-line voltage kept at the desired value during the whole programming operation. A spread as small as 70 mV was measured between the single-bit and 16-b programming cases     

A statistical model for SILC in flash memories

The reliability of flash memories is strongly. limited by the stress-induced leakage current (SILC), which leads to accelerated charge-loss phenomena in a few anomalous cells. Estimating the reliability of large flash arrays requires that physically-based models for the statistical distribution of SILC are developed. In this paper, we show a physical model for the leakage mechanism in thin oxides, which is able us to explain the anomalous leakage-conduction in tail cells. The physical model is then used for a quantitative evaluation of the SILC distribution in large flash arrays. The new model can reproduce the statistics of SILC for a wide range of tunnel-oxide thickness, and can provide a straightforward estimation of the reliability for large flash arrays.     

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10^-4 to 10^-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA     

A monolithic decode-drive circuit for magnetic memories

The highly replicated decode-drive circuitry of magnetic memories is being produced at a very low cost with batch-fabricated integrated-circuit technology. This has resulted from judiciously reconfiguring traditional circuit forms in order to optimize their fabrication. A new monolithic circuit function and its application are described. The circuit is used for low-cost high-speed 400-mA switching in magnetic memories. The functions of address decoding and timing control are also incorporated into the circuit. The address scheme employs no transformers and possesses the advantages of miniaturization. Details of the circuit configuration, topology, and packaging are described and illustrated.     

A novel high-speed sense amplifier for Bi-NOR flash memories

A novel high-speed current-mode sense amplifier is proposed for Bi-NOR flash memory designs. Program and erasure of the Bi-NOR technologies employ bi-directional channel FN tunneling with localized shallow P-well structures to realize the high-reliability, high-speed, and low-power operation. The proposed sensing circuit with advanced cross-coupled structure by connecting the gates of clamping transistors to the cross-coupled nodes provides excellent immunity against mismatch compared with the other sense amplifiers. Furthermore, the sensing times for various current differences and bitline capacitances and resistances are all superior to the others. The agreement between simulation and measurement indicates the sensing speed reaches 2ns for the threshold voltage difference of lower than 1 V at 1.8-V supply voltage even with the high threshold voltage of the peripheral CMOS transistors up to 0.8 V.     

A dual-page programming scheme for high-speed multigigabit-scaleNAND flash memories

To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture     

Optimized programming of multilevel flash EEPROMs

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 μm flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional Box-Waveform counterpart, allowing one to write a larger number of b/s. In particular at low programming speed ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mb/s in the conventional 1-b-per-cell scheme (and correspondingly higher values in the multilevel case). Instead, sixteen level schemes without program and verify do not seem practically feasible     

Charging simulations in nanocrystal quantum flash memories

The comprehension of the charging of a floating gate composed of nanocrystals (NCs) in a non-volatile flash memory is a real challenge. A few electrons tunnel from the channel of a metal-oxide-semiconductor transistor into the two-dimensional array of nanocrystals.A realistic three-dimensional model is proposed for electron tunneling into the floating gate. The energy subbands of the channel are explicitly included, together with the doping density. The model is solved thanks to a finite element method.Therefore many simulations can be carried out to better understand the relation between the tunneling times for charging a single NC, or the whole NC floating gate, and the geometrical parameters for example. Moreover a detailed statistical study concerning the dispersion of the relevant parameters can be led, helping the experimentalists to determine the optimal operating conditions of quantum flash memories.     

Reliability of HTO based high-voltage gate stacks for flash memories

We report on the excellent reliability performance of high-voltage (HV) gate stacks comprised of a thin thermal oxide and a thicker HTO layer. Time-to-breakdown of the developed stacks exceeded corresponding values for thermal HV oxides of the same thickness. Peculiarities of current relaxation in course of electrical stress tests are interpreted by injected charge trapping in HTO and new trap generation. Charge trapping in optimized HTO is low and guarantees reliable device operation.     

A multipage cell architecture for high-speed programming multilevelNAND flash memories

To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V_th of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 μs/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized