Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

一种新颖的全方位多扫描设计的测试压缩方法

提出了一种基于展开宽度可调的解压缩技术和X-压缩的多扫描电路的测试压缩方法。采用可变宽度的扫描链解压缩方法，对测试输入进行解压缩，且对于测试响应，结合了X-压缩的优点，测试响应整合器最小化故障被屏蔽的概率，扫描链的结构采取广播扫描模式。在此基础上对其改进，使其可同时处理取值相反的触发器。两种工作模式（串行模式和并行模式）可进一步处理剩余的紧凑的触发器值。提出的测试压缩算法的优点是：可节省测试设备的存储需求，减少测试输入输出引脚数和测试通道数，降低测试应用时间，从而全面提高测试激励数据和测试响应数据的压缩率。实验结果证明了该算法与以往算法相比较的优势。     

Test Data Compression Using Selective Encoding of Scan Slices

We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices of test data that are fed to the scan chains in every clock cycle. To drive $N$ scan chains, we use only $c$ tester channels, where $c=lceillog_2(N+1)rceil+2$ . In the best case, we can achieve compression by a factor of $N/c$ using only one tester clock cycle per slice. We derive a sufficient condition on the distribution of care bits that allows us to achieve the best-case compression. We also derive a probabilistic lower bound on the compression for a given care-bit density. Unlike popular compression methods such as Embedded Deterministic Test (EDT), the proposed approach is suitable for IP cores because it does not require structural information for fault simulation, dynamic compaction, or interleaved test generation. The on-chip decoder is small, independent of the circuit under test and the test set, and it can be shared between different circuits. We present compression results for a number of industrial circuits and compare our results to other recent compression methods targeted at IP cores.      

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s _max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s _max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s _max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping

In order to further reduce test data storage and test power of deterministic BIST based on scan slice overlapping, this paper proposes a novel optimization approach. Firstly, a san cell grouping method considering layout constraint is introduced to shorten the scan chain. Secondly, a novel scan cell ordering approach considering layout constraint is proposed to optimize the order of scan chain. Lastly, the authors propose an improved test pattern partition algorithm which selects the scan slice with the most specified bits as the first scan slice of the current overlapping block. Experimental results indicate that the proposed optimization approach significantly reduces the scan-in transitions and test data storage by 73%–93% and 60%–87%, respectively.     

An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

The emergence of the nanometer scale integration technology made it possible for systems-on-a-chip, SoC, design to contain many reusable cores from multiple resources. This resulted in higher complexity SoC testing than the conventional VLSI. To address this increase in design complexity in terms of data-volume and test-time, several compression methods have been developed, employed and proposed in the literature. In this paper, we present a new efficient test vector compression scheme based on block entropy in conjunction with our improved row-column reduction routine to reduce test data significantly. Our results show that the proposed method produces much higher compression ratio than all previously published methods. On average, our scheme scores nearly 13% higher than the best reported results. In addition, our scheme outperformed all results for each of the tested circuits. The proposed scheme is very fast and has considerable low complexity.     

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture     

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

Various compression methods have been proposed for tackling the problem of increasing test-data volume of contemporary, core-based systems. Despite their effectiveness, most of the approaches that are based on classical codes (e.g., run-lengths, Huffman) cannot exploit the test-application-time advantage of multiple-scan-chain cores, since they are not able to perform parallel decompression of the encoded data. In this paper, we take advantage of the inherent parallelism of Huffman decoding and we present a generalized multilevel Huffman-based compression approach that is suitable for cores with multiple scan chains. The size of the encoded data blocks is independent of the slice size (i.e., the number of scan chains), and thus it can be adjusted so as to maximize the compression ratio. At the same time, the parallel data-block decoding ensures the exploitation of most of the scan chains' parallelism. The proposed decompression architecture can be easily modified to suit any Huffman-based compression scheme.     

基于ATE的电源芯片Multi-Site测试设计与实现

介绍了电源芯片的多Site测试设计与实现。基于CTA8280测试系统,通过对芯片CP(晶圆测试)要求进行分析,设计了8 Site测试电路外围,能够实现对晶圆进行8 Die并行测试。测试结果显示,该方案能够有效提升该电源芯片的测试效率,降低测试成本。     

Scan Latch Design for Test Applications

This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

A New Scan Partition Scheme for Low‐Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.     

一种低功耗BIST测试产生器方案

低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案，该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑，对LFSR的输出和时钟进行调整，从而得到了准单输入跳变的测试向量集，使得待测电路的平均功耗大大降低，给出了以ISCAS'85/89部分基准电路为对象的实验结果，电路的平均测试功耗降幅在54．4％－98．0％之间，证明了该方案的有效性。     

一种降低OFDM峰均比的编码方法

讨论了一种降低正交频分复用(OFDM)系统峰均比的分组编码方法.对于4载波OFDM系统,通过对已有QPSK调制下具有最小峰均比(PAR)的码字进行分析,表明了能使峰均比降低至少3 dB的码字所满足的相位关系,并以此为基础,研究推广了这类码字在M-PSK调制下的一种一般获取过程.对于子载波个数增大的OFDM系统,讨论了以4载波编码方法为基础降低峰均比的办法,对其进行了理论分析并给出了仿真研究.仿真结果表明文中编码方法不仅能有效降低OFDM系统的PAR,而且具有一定的纠错能力.     

多链扫描可测性设计中扫描链的选取

本文提出了多链扫描可测性设计中扫描链的构造方法．根据电路的规模、输人／输出管脚数及测试时间的要求确定扫描链个数，引人临界时间的概念，采用动态编程的方法确定每条链中的扫描触发器．采用该方法，计算速度比传统方法显著提高，同时节省了存储空间．