Suppression of twin formation in CdTe(111)B epilayers grown by molecular beam epitaxy on misoriented Si(001)

CdTe(lll)B layers have been grown on misoriented Si(001). Twin formation inside CdTe(lll)B layer is very sensitive to the substrate tilt direction. When Si(001) is tilted toward [110] or [100], a fully twinned layer is obtained. When Si(001) is tilted toward a direction significantly away from [110], a twin-free layer is obtained. Microtwins inside the CdTe(111)B layers are overwhelmingly dominated by the lamellar twins. CdTe(111)B layers always start with heavily lamellar twinning. For twin-free layers, the lamellar twins are gradually suppressed and give way to twin-free CdTe(111)B layer. The major driving forces for suppressing the lamellar twinning are the preferential orientation of CdTe[11-2] along Si[1-10] and lattice relaxation. Such preferential orientation is found to exist for the CdTe(111)B layers grown on Si(001) tilted toward a direction between [110] and [100].     

在Si(211)衬底上分子束外延CdTe的剪切应变

利用高分辨率X射线衍射技术对分子束外延CdTe（211）B/Si（211）材料的CdTe外延薄膜进行了倒易点二维扫描,并通过获得的对称衍射面和非对称衍射面的倒易空间图,对CdTe缓冲层的剪切应变状况进行了分析.研究发现,对于CdTe/Si结构,随着CdTe厚度的增加,[1-1-1]、[01-1]两个方向的剪切角γ[1-1-1]和γ[01-1]都有变小的趋势,且γ[1-1-1]的大小约为γ[01-1]的两倍;对于CdTe/ZnTe/Si结构,ZnTe缓冲层的引入可以有效地降低CdTe层的剪切应变.     

CdTe/GaAs(111)B薄膜的MBE生长研究

采用分子束外延方法,在GaAs(111)B衬底上,生长CdTe薄膜,以求研制出用于液相外延生长碲镉汞(HgCdTe)薄膜的CdTe/GaAs(111)B复合衬底.通过理论分析和实验探索,优化了生长温度和Te/Cd束流比等重要生长参数,获得了质量较好的CdTe薄膜,再通过循环热处理,使CdTe/GaAs(111)B复合衬底的质量得到进一步的提高,X-射线回摆曲线半峰宽(FWHM)有明显的降低.为LPE-HgCdTe薄膜的生长打下了较好基础.     

HgTe/HgCdTe superlattices grown on CdTe/Si by molecular beam epitaxy for infrared detection

High-quality HgTe/CdTe superlattices (SLs) and device structures incorporating them were grown by molecular beam epitaxy (MBE) on CdTe/Si substrates. In-situ techniques, such as reflection, high-energy electron diffraction and spectroscopic ellipsometry, were extensively used to rigorously control the growth parameters. The full width at half maximum (FWHM) of x-ray double-crystal rocking curves (DCRCs) were 100–150 arcsec, comparable to those of HgCdTe alloys grown on the same type of substrates. The room-temperature Fourier transform infrared (FTIR) spectrum exhibits two-dimensional features characteristic of SLs. Trial devices in a p⁺-n⁻-n⁺ format were fabricated by diffusing gold in order to further evaluate the HgTe/CdTe SL performance. Gold diffusion was chosen to fabricate photovoltaic junctions in order to preserve the structural integrity of the SLs during the device processing. Though no attempt was made in the current study to optimize the junction properties by Au diffusion, this method has proven to be very useful for rapid preliminary evaluation. The measured spectral-response and detectivity data indicate the possibility to fabricate photovoltaic devices on an HgTe/CdTe SL, although further work is needed to optimize the p-n junction fabrication.     

3英寸CdTe/Si复合衬底外延技术研究

报道了采用分子束外延法,在3 in硅衬底上通过As钝化、ZnTe缓冲层生长、CdTe生长、周期性退火等工艺进行CdTe/Si复合衬底制备技术研究情况,采用光学显微镜、X射线高分辨衍射仪、原子力显微镜、红外傅里叶光谱仪和湿化学腐蚀等手段对碲化镉薄膜进行了表征,测试分析结果表明碲化镉薄膜的晶向得到了较好的控制,孪晶得到了抑...     

Si基大面积碲镉汞分子束外延研究

文章报道了Si基碲镉汞分子束外延(MBE)的最新研究进展。尝试用晶向偏角降低高界面应变能的方法,摸索大失配体系中位错的抑制途径,寻找位错密度与双晶半峰宽的对应关系,基本建立了外延材料晶体质量无损检测评价标准,并对外延工艺进行指导。通过上述研究,15~20μm Si基CdTe复合材料双晶半峰宽最好结果为54arcsec,对应位错密度(EPD)小于2×106/cm2,与相同厚度的GaAs/CdTe(211)双晶水平相当,达到或优于国际最好结果。获得的3 in 10μm Si基HgCdTe材料双晶半峰宽最好结果为51arcsec,目前Si基HgCdTe材料已经初步应用于焦平面中波320×240器件制备。     

Microstructural and optical characterization of CdTe(211)B/ZnTe/Si(211) grown by molecular beam epitaxy

CdTe layers have been grown by molecular beam epitaxy on 3 inch nominal Si(211) under various conditions to study the effect of growth parameters on the structural quality. The microstructure of several samples was investigated by high resolution transmission electron microscopy (HRTEM). The orientation of the CdTe layers was affected strongly by the ZnTe buffer deposition temperature. Both single domain CdTe(133)B and CdTe(211)B were obtained by selective growth of ZnTe buffer layers at different temperatures. We demonstrated that thin ZnTe buffer layers (<2 nm) are sufficient to maintain the (211) orientation. CdTe deposited at ∼300°C grows with its normal lattice parameter from the onset of growth, demonstrating the effective strain accommodation of the buffer layer. The low tilt angle (<1°) between CdTe[211] and Si[211] indicates that high miscut Si(211) substrates are unnecessary. From low temperature photoluminescence, it is shown that Cd-substituted Li is the main residual impurity in the CdTe layer. In addition, deep emission bands are attributed to the presence of As_Te and Ag_Cd acceptors. There is no evidence that copper plays a role in the impurity contamination of the samples.     

Si基CdTe复合衬底分子束外延研究

文章引入晶格过渡的Si/ZnTe /CdTe作为复合外延基底材料,以阻挡Si/HgCdTe之间大晶格失配产生的高密度位错。通过对低温表面清洁化、面极性控制和孪晶抑制等的研究,解决了Si基CdTe分子束外延生长中诸多的技术难题。在国内首次采用分子束外延(MBE)的方法获得了大面积的Si基CdTe复合衬底材料,对应厚度为4～4. 4μm Si/CdTe (211)样品双晶半峰宽的统计平均结果为83弧秒,与相同厚度的GaAs/CdTe (211)双晶平均水平相当。     

Synchrotron white beam x-ray topography analysis of MBE grown CdTe/CdTe (111)B

The structural quality of CdTe(111)B substrates and MBE grown CdTe epilayers is examined with synchrotron white beam x-ray topography (SWBXT). Reflection SWBXT indicates that CdTe substrates with comparable x-ray double crystal rocking curve full width at half maximum values can have radically different defect microstructures, i.e. dislocation densities and the presence of inclusions. Dislocation mosaic structures delineated by SWBXT are consistent with the distribution of etch pits revealed by destructive chemical etch pit analysis. Direct one-to-one correspondence between distinct features of the topographic image and individual etch pits is demonstrated. Clearly resolved images of individual dislocations are obtained by carrying out transmission SWBXT. Our investigation demonstrates how, the extent of twinning in a CdTe epilayer is strongly influenced by the quality of the defect microstructure, and how dislocations propagate from an inclusion.     

偏转角(211)Si基CdTe复合衬底研究

晶面偏角是提高(211) Si基CdTe复合衬底质量的方法之一。通过对偏转角Si基CdTe复合衬底分子束外延工艺的研究,发现2°和3°偏转角(211)Si基CdTe复合衬底在晶体质量方面优于标准(211)Si基CdTe复合衬底,是未来提高Si基CdTe复合衬底质量的新方向。     

Improved morphology and crystalline quality of MBE CdZnTe/Si

We report on continuing efforts to develop a reproducible process for molecular beam epitaxy of CdZnTe on three-inch, (211) Si wafers. Through a systematic study of growth parameters, we have significantly improved the crystalline quality and have reduced the density of typical surface defects. Lower substrate growth temperatures (∼250–280°C) and higher CdZnTe growth rates improved the surface morphology of the epilayers by reducing the density of triangular surface defects. Cyclic thermal annealing was found to reduce the dislocation density. Epilayers were characterized using Nomarski microscopy, scanning electron microscopy, x-ray diffraction, defect-decoration etching, and by their use as substrates for HgCdTe epitaxy.     

分子束外延CdTe（211）B／Si复合衬底材料

报道了用MBE的方法，在3英寸Si衬底上制备ZnTe／CdTe（211）B复合衬底材料的初步研究结果，该研究结果将能够直接应用于大面积Si基HgCdTe IRFPA材料的生长．经过Si（211）衬底低温表面处理、ZnTe低温成核、高温退火、高温ZnTe、CdTe层的生长研究，用MBE方法成功地获得了3英寸Si基ZnTe／CdTe（211）B复合衬底材料．CdTe厚度大于10μm，XRD FWHM平均值为120arc sec，最好达到100arc sec，无（133）孪晶和其他多晶晶向．     

CdTe/Si复合衬底Ex-situ退火研究

复合衬底CdTe/ZnTe/Si的晶体质量是导致随后外延的HgCdTe外延膜高位错密度的主要原因之一,因此如何提高复合衬底CdTe/Si晶体质量是确保硅基碲镉汞走上工程化的关键所在。降低复合衬底CdTe/Si位错密度方法一般有:生长超晶格缓冲层、衬底偏向、In-situ退火和Ex-situ退火等,本文主要研究Ex-situ退火对复合衬底CdTe/Si晶体质量的影响。研究表明复合衬底经过Ex-situ退火后位错密度最好值达4.2×105cm-2,双晶半峰宽最好值达60arcsec。     

Molecular beam epitaxy grown long wavelength infrared HgCdTe on Si detector performance

The use of silicon as a substrate alternative to bulk CdZnTe for epitaxial growth of HgCdTe for infrared (IR) detector applications is attractive because of potential cost savings as a result of the large available sizes and the relatively low cost of silicon substrates. However, the potential benefits of silicon as a substrate have been difficult to realize because of the technical challenges of growing low defect density HgCdTe on silicon where the lattice mismatch is ∼19%. This is especially true for LWIR HgCdTe detectors where the performance can be limited by the high (∼5×10⁶ cm⁻²) dislocation density typically found in HgCdTe grown on silicon. We have fabricated a series of long wavelength infrared (LWIR) HgCdTe diodes and several LWIR focal plane arrays (FPAs) with HgCdTe grown on silicon substrates using MBE grown CdTe and CdSeTe buffer layers. The detector arrays were fabricated using Rockwell Scientific’s planar diode architecture. The diode and FPA and results at 78 K will be discussed in terms of the high dislocation density (∼5×10⁶ cm²) typically measured when HgCdTe is grown on silicon substrates.     

Comparison of MBE Growth of InSb on Si (001) and GaAs (001)

We describe the epitaxial growth of InSb films on both Si (001) and GaAs (100) substrates using molecular-beam epitaxy and discuss the structural and electrical properties of the resulting films. The complete 2 μm InSb films on GaAs (001) were grown at temperatures between 340°C and 420°C and with an Sb/In flux ratio of approximately 5 and a growth rate of 0.2 nm/s. The films were characterized in terms of background electron concentration, mobility, and x-ray rocking curve width. Our best results were for a growth temperature of 350°C, resulting in room-temperature mobility of 41,000 cm²/V s.  For the growth of InSb on Si, vicinal Si(001) substrates offcut by 4° toward (110) were used. We investigated growth temperatures between 340°C and 430°C for growth on Si(001). In contrast to growth on GaAs, the best results were achieved at the high end of the range of T _S =  C, resulting in a mobility of 26,100 cm²/V s for a 2 μm film. We also studied the growth and properties of InSb:Mn films on GaAs with Mn content below 1%. Our results showed the presence of ferromagnetic ordering in the samples, opening a new direction in the diluted magnetic semiconductors.     

Synchrotron X-Ray photoconductor detector arrays made on MBE grown CdTe

We have been fabricating x-ray photoconductor linear array detectors using molecular beam epitaxially (MBE) grown (lll)B undoped CdTe layers on (100) Si substrates. A novel technique was developed to remove the Si and to mount the fragile MBE grown CdTe layers onto insulating ceramic substrates. 256 channel linear photoconductor array devices were fabricated on the resulting CdTe layers. The resistivity of MBE (lll)B CdTe was high (>108 \cm) enough to utilize the material for low energy (8 ~ 25 keV) x-ray detectors. The stability of the detectors are satisfactory, and they were tested at room temperature routinely for over a year. The performance of the photoconductor was greatly improved when the detector was cooled to 230K. Due to its reduced dark current at low temperatures, the dynamic range of the detector response increased to nearly four decades at 230K.     

在Si(211)衬底上分子束外延CdTe的晶格应变

文章利用高分辨率X射线衍射技术对分子束外延CdTe（211）B/Si（211）材料的CdTe外延薄膜进行了倒易点二维扫描,并通过获得的对称衍射面和非对称衍射面的倒易空间图,对CdTe外延层的剪切应变和正应变状况进行了分析.研究发现,对于CdTe/Si结构,随着CdTe厚度的增加,[1-1-1]、[01-1]两个方向的剪切角γ[1-1-1]和λ[01-1]都有变小的趋势,且γ[1-1-1]的大小约为γ[01-1]的两倍;对于CdTe/ZnTe/Si,ZnTe缓冲层的引入可以有效地降低CdTe层的剪切应变.CdTe层的正应变表现为张应变,主要来源于CdTe和Si的热膨胀系数存在差异,而在从生长温度280℃降至室温20℃的过程产生的热应变.     

HgCdTe/CdTe/Si infrared photodetectors grown by MBE for near-room temperature operation

Conventional HgCdTe infrared detectors need significant cooling in order to reduce noise and leakage currents resulting from thermal generation and recombination processes. Although the need for cooling has long been thought to be fundamental and inevitable, it has been recently suggested that Auger recombination and generation rates can be reduced by using the phenomena of exclusion and extraction to produce nonequilibrium carrier distributions. The devices with Auger suppressed operation requires precise control over the composition, and donor and acceptor doping. The successful development of the molecular beam epitaxy (MBE) growth technique for multi-layer HgCdTe makes it possible to grow these device structures. Theoretical calculations suggest that the p n+ layer sequence is preferable for near-room temperature operation due to longer minority carrier lifetime in lightly doped p-HgCdTe absorber layers. However, because the low doping required for absorption and nonequilibrium operation is easier to achieve in n-type materials, and because Shockley-Read centers should be minimized in order to obtain the benefits of Auger suppression, we have focused on p⁺ n structures. Planar photodiodes were formed on CdTe/Si (211) composite substrates by As implantation followed by a three step annealing sequence. Three inch diameter Si substrates were employed since they are of high quality, low cost, and available in large areas. Due to this development, large area focal plane arrays (FPAs) operated at room temperature are possible in the near future. The structures were characterized by FTIR, x-ray diffraction, temperature dependent Hall measurements, minority carrier lifetimes by photoconductive decay, and in-situ ellipsometry. To study the relative influence of bulk and surface effects, devices with active areas from 1.6 10⁻⁵ cm² to 10⁻³ cm² were fabricated. The smaller area devices show better performance in terms of reverse bias characteristics indicating that the bulk quality could be further improved. At 80 K, the zero bias leakage current for a 40 m 40 m diode with 3.2 m cutoff wavelength is 1 pA, the R₀A product is 1.1 10⁴-cm² and the breakdown voltage is in excess of 500 mV. The device shows a responsivity of 1.3 10⁷ V/W and a 80 K detectivity of 1.9 10¹¹ cm-Hz^1/2/W. At 200 K, the zero bias leakage current is 5 nA and the R₀A product 2.03-cm², while the breakdown voltage decreases to 40 mV.     

Dual-band infrared detectors made on high-quality HgCdTe epilayers grown by molecular beam epitaxy on CdZnTe or CdTe/Ge substrates

In this paper, we present all the successive steps for realizing dual-band infrared detectors operating in the mid-wavelength infrared (MWIR) band. High crystalline quality HgCdTe multilayer stacks have been grown by molecular beam epitaxy (MBE) on CdZnTe and CdTe/Ge substrates. Material characterization in the light of high-resolution x-ray diffraction (HRXRD) results and dislocation density measurements are exposed in detail. These characterizations show some striking differences between structures grown on the two kinds of substrates. Device processing and readout circuit for 128×128 focal-plane array (FPA) fabrication are described. The electro-optical characteristics of the devices show that devices grown on Ge match those grown on CdZnTe substrates in terms of responsivity, noise measurements, and operability.     

Direct growth of CdTe on (100), (211), and (111) Si by metalorganic chemical vapor deposition

CdTe epilayers were grown directly on (100), (211), and (111) silicon substrates by metalorganic chemical vapor deposition (MOCVD). The crystallinity and the growth orientation of the CdTe film were dependent on the surface treatment of the Si substrate. The surface treatment consisted of exposure of the Si surface to diethyltelluride (DETe) at temperatures over 600°C prior to CdTe growth. Direct growth of CdTe on (100) Si produced polycrystalline films whereas (lll)B single crystals grew when Si was exposed to DETe prior to CdTe growth. On (211) Si, single crystal films with (133)A orientation was obtained when grown directly; but produced films with (211)A orientation when the Si surface was exposed to DETe. On the other hand, only (lll)A CdTe films were possible on (111) Si, both with and without Te source exposure, although twinning was increased after exposure. The results indicate that the exposure to a Te-source changes the initial growth stage significantly, except for the growth on (111) Si. We propose a model in which a Te atom replaces a Si atom that is bound to two Si atoms.