Switching losses in a GTO inverter for induction heating

The application of gate-turn-off thyristors (GTOs) to parallel resonant inverters for induction heating is investigated. Three different modes of operation of the GTOs are explained and tested in a test circuit. The optimum mode is selected by switching loss measurement. It is shown that due to the small inductance in the commutation circuit, the gate-assisted turn-off technique leads to very high turn-on losses and is not the optimum way to drive the GTO in this application. However, it can be used under different conditions in order to reduce turn-off losses. It is suggested that a mixed turn-off of the devices by both gate action and natural commutation is the optimum mode of operation. Then, the load is driven at unity power factor. In this mode of operation, no snubbers are necessary in principle. A small capacitor in parallel to the GTO is recommended for only the staring procedure. An estimation of the total power loss in the GTOs leads to the result that the GTO tested can be operated at frequencies between 10 kHz and 20 kHz with a reasonable inverter efficiency     

A new ultra-wideband fractal monopole antenna

The paper focuses on the peculiar dynamic behaviour of the recently developed 8 mm² TO-220-packaged, high-voltage, double-interdigitated (or rwo interdigi-tation levels—TIL) GTO thyristor. This novel power device was rated under both slightly and heavily inductive resistive loads, i.e. close to the real conditions encountered in practical power circuits employing GTO thyristors. Emphasis is laid on the ability of TIL GTOs to switch safely, with minimum power losses, a certain amount of anode current under high-voltage conditions and high commutation frequencies. The merits of TIL GTO thyristors are analysed in terms of their reliability and switching efficiency, which include the total power losses (conduction and switching losses), turn-on and turn-off gains and the switching speed. It is shown that thanks to their built-in self-protective features, these novel GTOs possess an enhanced current-handling capability at commutation frequencies up to 50kHz under extremely tough load conditions. The main implications of the results for power applications are outlined.     

Symmetric GTO and snubber component characterization in PWMcurrent-source inverters

The pulsewidth-modulated (PWM) current-source inverter (CSI) used in AC motor drive applications can be implemented with symmetric gate turn-off thyristors (GTOs). One of the major difficulties in the optimization of the GTO switch and the snubber components of the inverter is the variation in different switching conditions encountered during normal operation. Past work has concentrated on the GTO and snubber components in voltage-source applications, where commutation of the GTO device is an independent process and does not affect the operation of the other inverter devices. This paper proposes the characterization of the GTO and the snubber components by formulation of the CSI equivalent circuit during the device commutation period. From the equivalent circuit, the state equations are derived, thereby obtaining accurate voltage and current waveforms of the GTO and associated snubbers. From the analysis, the component power loss can be calculated and optimization performed. Simulation results are verified by using both a laboratory prototype and medium-voltage drive system     

Efficiency of gate control in double-interdigitated (TIL) GTO thyristors

The research reported in this work was focused on the efficiency of gate control during turn-off in the recently developed double-interdigitated (TIL) GTO thyristors. The 8 mm² area, TO-220 packaged, high voltage test devices were investigated under both current and voltage input conditions. The main monitored parameters were: the peak turn-off gain K_off(max), the components of the turn-off time and the gate pulse width t_gr. During the tests the TIL GTOs were driven up to an anode current i_T = 50 A, a value equal to the non-repetitive peak on-state current (I_TSM) of these thyristors.The performed investigations have shown that these novel GTO devices possess a good efficiency of gate control expressed by: 1) low power consumption by the gate under both current and voltage drive conditions; 2) extremely high turn-off gain K_off(max), which is an increasing function of the anode current in a wide range of gate signals amplitudes and durations; 3) fast turn-off of large amounts of anode current with relatively short gate pulse widths; 4) substantial reduction of the storage time t_s and fall time t_f through adequate current or voltage drive. Design/behavioral details are given, which are useful in the implementation of the TIL concept in GTOs and other power switching devices, such as the bipolar transistors.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.     

Gate-assisted reverse and forward recovery of high-power GTOs inseries resonant DC-link inverters

The series resonant DC-link inverter is an attractive circuit topology for interfacing a DC current with a three-phase AC system. It uses gate turn-off thyristors (GTOs) as semiconductor switches. The conventional solution requires an additional series diode to perform the turn off process and to enable forward recovery of the GTO. This paper uses a single GTO along with a special gate drive to provide reverse and forward recovery. A new device testing circuit was designed to create the same electrical and thermal stresses as in a series resonant DC-link inverter. Experimental results using 2000 A GTOs at 26 kHz switching frequency demonstrate that the total device losses are reduced, while the hold-off time is slightly increased. The new single-device solution makes resonant switching attractive for very high-power applications     

Effect of Gate-Drive Circuits on GTO Thyristor Characteristics

This paper deals with the effects of gate drive circuits on turn-on and turn-off characteristics of GTO thyristors. The turn-on methods are outlined and their effects on switching performance are discussed. The turn-off characteristics and the failure modes associated with the storage, fall, tailing, and avalanche periods are presented. Solutions to failure modes are outlined. Both direct and indirect gate drive circuits are presented. The effects of ideal voltage source and series insertion of gate inductance to storage, fall, tailing, and avalanche breakdown period of the GTO thyristors are studied and compared. The suitability of using certain types of gate drive circuits for certain GTO thyristors is discussed.     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—I. Analysis and design

A rigorous analysis of the novel two-interdigitation levels gate turn-off thyristors (TIL GTOs) is performed with the aim of increasing their current-handling capability up to their limits. A closed form relationship correlating the maximum controllable anode current I_ATO with the peculiar geometry of the TIL pattern and the main technological parameters is obtained. Design rules with general validity are set out for the worst premises and correlated with the physics underlying the peculiar behaviour of TIL GTOs in various modes of operation. Based on the advanced three-transistor model of the TIL GTO structure, the basic theory underlying the device behaviour in the ‘on’ state is developed. The mechanisms of the current balancing between the two types of p-n-p-n sections (standard and quasi-non-regenerative) constituting the TIL GTO structure are disclosed. The broad implications of the current balancing on the current-handling capability of devices are presented in detail. The optimized design criteria were applied to 4 × 4 mm area, TO-220-packed TIL GTOs. The projected value of I_ATO in the worst case is 45 A, which would be the highest value of I_ATO ever reported in the literature for this class of GTOs (identical device area and case).     

Demonstration of compact solid-state opening and closing switchutilizing GTOs in series

A compact opening and closing solid-state switch was designed, constructed, and demonstrated. The switch repetitively switches over 4 MW of peak power and yet is only 0.45 m by 0.12 m by 0.32 m and has a mass of 13 kg. The switch uses commercially available gate turn-off thyristors (GTOs), arranged in series to enable the collected devices to switch a voltage five times the rating of an individual device. The system uses commercially available components exclusively, yet takes advantage of state-of-the-art components. These include multilayer ceramic capacitors which are arrayed to produce a snubber capacitor, and small high-voltage isolated power transformers that protect each of the seven GTO stages from breakdown damage via their power supplies. Each stage is controlled via a fiber-optic link, and turn-on and turn-off times are adjustable for each of the seven stages. System dV/ dt exceeded 1 kV/μs and system di/dt exceeded 200 A/μs, for both turn-on and turn-off. The system was only limited in the amount of power it could switch by thermal considerations. A much higher power could be switched if there were advanced cooling. The cooling devices were quite modest, in that this was only a demonstration of the principle     

An economical four-quadrant GTO converter and its application to DCdrives

A four-quadrant gate turn-off (GTO) power converter employing a single six-GTO bridge and four thyristors as reversing switches is described. Such a four-quadrant converter is economical compared to a dual-converter employing two bridges, each with six GTOs. A four-quadrant DC motor drive employing the proposed converter and closed-loop speed control with an inner current control loop is also presented. The controllers are designed using symmetric optimization. Experimental results with a 3 HP DC motor are given for steady-state and transient responses of the drive. A comparative study of the present four-quadrant drive and the one reported earlier is also presented     

Zero-current and zero-voltage soft-transition commutation cell for PWM inverters

This paper presents a universal auxiliary commutation cell for pulse-width modulated (PWM) inverters termed zero current and zero voltage transition (ZCZVT) commutation cell. It provides zero current and zero voltage commutation, simultaneously, during main power devices turn-on and turn-off, with controlled di/dt and dv/dt. As a result, commutations of the main power devices occur without any losses. This unique characteristic is not achieved by any other soft-switching commutation cell for inverters hitherto presented in the literature, making it a strong candidate for use in low-power (MOSFET), medium-power (IGBT) or high-power applications (GTO, thyristor). Furthermore, reverse recovery losses of main diodes are minimized and auxiliary switches commutate at zero current. To demonstrate the operation of the proposed universal auxiliary commutation cell, a ZCZVT PWM full-bridge inverter is analyzed. To evaluate the operation of the auxiliary circuit in different conditions, prototypes with both IGBTs and MOSFETs for different output powers levels were implemented and their performances compared. Experimental results confirm that there is no overlap between main switch current and voltage, and that waveform ringing is practically eliminated.     

Numerical modeling of gate turn-off thyristor using SICOS

A numerical model of gate turn-off thyristors (GTOs) is presented. The concept of a controlled switch realized by a controlled current source is first introduced. Using this basic model, an equivalent circuit for the GTO is given. Using the GTO characteristics given by manufacturers, the equations connected with all the parameters of the equivalent circuit are deduced, and all of the parameters are determined. A sample study is presented. Simulation of this numerical model with the SICOS program gave results in accordance with the experiment     

A new gate drive circuit for high-speed operation of GTO thyristors

This paper presents a new gate turn-off drive circuit for GTO thyristors, which can accomplish faster turn-off switching for high-speed operation of the GTO. The switching characteristics of GTO's can be improved by use of the gate drive circuit that is able to make a very high rate of the negative gate current. The major disadvantage of the conventional gate turn-off driving technique is that it has a difficulty in realizing higher negative di_G/dt due to the maximum reverse gate-cathode voltage and the stray inductances within the gate turn-off drive circuit. This paper shows that this problem can be overcome by adding another gate turn-off drive circuit to the conventional gate turn-off drive circuit. Simulation and experimental results in conjunction with chopper circuit verify the performance of the proposed gate drive circuit     

Characterization of GTOs under different modes of zero currentswitching

Several papers have described the use of GTOs in zero current switching (ZCS) applications, with the goal of increasing the frequency range for medium- and high-power converters. Zero current switching with GTOs can be applied in series and parallel resonant converters, as well as in PWM inverters with commutation aid networks. The voltage and current waveforms at the devices differ in each of these applications, and different modes of ZCS can be identified. In this paper, a comparative view of the behavior and characteristics of the GTO in the different modes of ZCS is presented. The variety of ZCS waveforms is described and transferred into a unifying schematic. The behavior of GTOs in the different modes of operation is characterized, and requirements to the circuit environment are pointed out. The relations between the most important circuit parameters and some of the device waveform parameters are investigated experimentally     

Turn-On Principles of the MOS-GTO

MOS-GTO's (GTO thyristors which are turned off by the action of a MOS-gate) represent a new generation of controllable thyristors offering considerable advantages in turn-off behavior as compared to conventional GTO's. However, MOS-GTO's generally require one control electrode for turn-on and another control electrode for turn-off, which might be regarded as a disadvantage. It is shown that in MOS-GTO's with a p-channel cathode structure it is possible to turn the thyristor on and off by controlling just one MOS gate electrode. As a triggering current for turn-on, the MOS capacitor charging current is used.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

A novel gate—Cathode configuration with two interdigitation levels for GTO thyristors

A new gate-cathode concept leading to a substantial improvement of the main parameters of the gate turn-off (GTO) thyristors has been developed and successfully tested on medium power devices. The distinctive feature of the novel pattern with two interdigitation levels (TIL) consists in its unique ability to bring under designer's control the processes of sweeping-out of the stored charge and of the anode current squeezing.     

Nonlinear capacitors in snubber circuits for GTO thyristors

Many applications with GTO thyristors require snubber circuits, at least for, turn-off. In achieving high switching frequencies there are conflicting design criteria for the snubber capacitor-losses versus timing conditions. Improvements to this situation are expected by employing nonlinear capacitors. Features of snubber circuits with nonlinear capacitors are described, and experimental results obtained from 50 A and 90 A GTO thyristors are discussed     

Characteristics of TIL GTO thyristors using no lifetime killers

The investigation reported in this work was focused on the main characteristics of the recently developed two interdigitation level (TIL) gate turn-off (GTO) thyristors, which use neither lifetime killers nor anode shorts. The advantages of these TIL GTO's with low on-state losses are outlined in comparison with their identical, yet gold-doped, counterparts. It is shown that, except for the turn-off time, the main electrical characteristics of TIL GTO's using no induced recombination centers are superior to those of similar gold-doped devices. The current-handling capability of the former under tough electrothermal ratings is also better than that of gold-doped devices up to a commutation frequency of 5 kHz. The results of this work demonstrated that sought-for benefits could be obtained in TIL GTO's which use neither induced recombination centers nor anode shorts.