Micropipe and dislocation density reduction in 6H-SiC and 4H-SiC structures grown by liquid phase epitaxy

We investigated silicon carbide (SiC) epitaxial layers grown by liquid phase epitaxy (LPE). The layers were grown on 6H-SiC and 4H-SiC well-oriented (0001) 35 mm diameter commercial wafers as well as on 6H-SiC Lely crystals. A few experiments were also done on off-axis 6H-SiC and 4H-SiC substrates. Layer thickness and growth rate ranged from 0.5 to 50 microns and 0.5 to 10 μm/h, respectively. Layers were investigated by x-ray diffraction, x-ray topography, and selective chemical etching in molten KOH. It was found that dislocation and micropipe density in LPE grown epitaxial layers were significantly reduced compared with the defect densities in the substrates.     

Strain relief in epitaxial HgCdTe by growth on a reticulated substrate

In nearly all cases when an epitaxial layer of HgCdTe is grown on a CdZnTe substrate, there will be a finite lattice mismatch due to the lack of precise control over the ZnTe mole fraction. This leads to strains in the layer, which can be manifested in one or more ways: (1) as misfit dislocations near the interface, (2) as threading dislocations, (3) as surface topographical textures, and (4) as cross-hatch lines seen by x-ray topography. We have found that much of the strain can be relieved by growing on a reticulated substrate. Specifically, when the substrate has been etched to form mesas prior to growth of the layer, the resulting layer on the tops of the mesas shows evidence of significantly reduced strain. CdZnTe substrates oriented (111)A were prepared with two sets of mesas on 125 μm centers and 60 μm centers, and with other planar areas remaining for comparison. From a Hg melt, a layer of LWIR HgCdTe was grown about 16 μm thick on each substrate. Nomarski microscopy showed that the layers on the mesa tops were extremely flat, showing no sign of curvature or surface texture. X-ray topography showed no cross hatch on the mesa tops, while the usual cross hatch appeared in the planar regions. The LPE layer extended laterally beyond the edges of the original mesa because of faster growth in non-(111) directions. Samples were cleaved and examined in cross section. The linear density of etch pits seen in the cross section near the substrate, which represent misfit dislocations, was three times lower in the layer on the mesas than in the layer in the unpatterned region, although both regions have the same layer/substrate lattice mismatch. When an epilayer is grown on an unpatterned wafer (the conventional approach), the growth in any small region is confined laterally by the growing layer in the neighboring regions. However, when growth occurs on a reticulated surface, the lateral confinement is removed, providing strain relief and fewer defects.     

Te-rich liquid phase epitaxial growth of HgCdTe on Si-based substrates

The growth of high quality (111)B oriented HgCdTe layers on CdZnTe/GaAs/Si and CdTe/Si substrates by Te-rich slider liquid phase epitaxy (LPE) is reported. Although the (111) orientation is susceptible to twinning, a reproducible process yielding twin-free layers with excellent surface morphology has been developed. The electrical properties and dislocation density in films grown on these substrates are comparable to those measured in HgCdTe layers grown on bulk CdTe substrates using the same LPE process. This is surprising in view of the large lattice mismatch that exists in these systems. We will report details of both the substrate and HgCdTe growth processes that are important to obtaining these results.     

碳化硅衬底外延石墨烯

通过高温热解法和化学气相沉积(CVD)法在SiC(0001)衬底外延石墨烯。采用光学显微镜、原子力显微镜、扫描电子显微镜、喇曼光谱、X射线光电子能谱和霍尔测试系统对样品进行表征,并对比了两种不同生长方法对石墨烯材料的影响以及不同的成核机理。结果表明,高温热解法制备的石墨烯材料有明显的台阶形貌,台阶区域平坦均匀,褶皱少,晶体质量取决于SiC衬底表面原子层,电学特性受衬底影响大,迁移率较低。CVD法制备的石墨烯材料整体均匀,褶皱较多,晶体质量更好。该方法制备的石墨烯薄膜悬浮在SiC衬底表面,与衬底之间为范德华力连接,电学特性受衬底影响小,迁移率较高。     

碲锌镉晶体的X射线衍射形貌与腐蚀形貌

碲锌镉晶体中存在着各种典型晶体缺陷,其缺陷研究一直倍受关注,X射线衍射形貌术是一种非破坏性地研究晶体材料结构完整性、均匀性的有效方法.采用反射式X射线衍射形貌术对碲锌镉衬底的质量进行了研究,并将衬底的X射线衍射形貌与Everson腐蚀形貌进行了对比分析,碲锌镉衬底的X射线衍射形貌主要有六种特征类型,分别对应不同的晶体结构或缺陷,包括均匀结构、镶嵌结构、孪晶、小角晶界、夹杂、表面划伤,对上述特征类型进行了详细的分析.目前,衬底的X射线衍射形貌主要以均匀结构类型为主,划伤和镶嵌结构缺陷基本已消除,存在的晶体缺陷主要以小角晶界为主.通过对比分析碲锌镉衬底和液相外延碲镉汞薄膜的X射线衍射形貌,发现小角晶界等晶体结构缺陷会延伸到外延层上,碲锌镉衬底质量会直接影响碲镉汞外延层的质量,晶体结构完整的衬底是制备高质量碲镉汞外延材料的基础.     

Threading and misfit-dislocation motion in molecular-beam epitaxy-grown HgCdTe epilayers

Lattice mismatch between the substrate and the absorber layer in single-color HgCdTe infrared (IR) detectors and between band 1 and band 2 in two-color detectors results in the formation of crosshatch lines on the surface and an array of misfit dislocations at the epi-interfaces. Threading dislocations originating in the substrate can also bend into the interface plane and result in misfit dislocations because of the lattice mismatch. The existence of dislocations threading through the junction region of HgCdTe IR-photovoltaic detectors can greatly affect device performance. High-quality CdZnTe substrates and controlled molecular-beam epitaxy (MBE) growth of HgCdTe can result in very low threading-dislocation densities as measured by the etch-pit density (EPD ∼ 10⁴cm⁻²). However, dislocation gettering to regions of high stress (such as etched holes, voids, and implanted-junction regions) at elevated-processing temperatures can result in a high density of dislocations in the junction region that can greatly reduce detector performance. We have performed experiments to determine if the dislocations that getter to these regions of high stress are misfit dislocations at the substrate/absorber interface that have a threading component extending to the upper surface of the epilayer, or if the dislocations originate at the cap/absorber interface as misfit dislocations. The preceding mechanisms for dislocation motion are discussed in detail, and the possible diode-performance consequences are explored.     

Investigation of Ti/Al and TiN/Al thin films as the stable ohmic contact for p-type 4H-SiC

Interfacial reactions, surface morphology, and current-voltage (I-V) characteristics of Ti/Al/4H-SiC and TiN/Al/4H-SiC were studied before and after high-temperature annealing. It was observed that surface smoothness of the samples was not significantly affected by the heat treatment at up to 900°C, in contrast to the case of Al/SiC. Transmission electron microscopy (TEM) observation of the Ti(TiN)/Al/SiC interface showed that Al layer reacted with the SiC substrate at 900°C and formed an Al-Si-(Ti)-C compound at the metal/SiC interface, which is similar to the case of the Al/SiC interface. The I-V measurement showed reasonable ohmic properties for the Ti/Al films, indicating that the films can be used to stabilize the Al/SiC contact by protecting the Al layer from the potential oxidation and evaporation problem, while maintaining proper contact properties.     

CdZnTe中富碲沉积相缺陷引起的液相外延HgCdTe薄膜表面缺陷

为了研究液相外延碲镉汞薄膜表面缺陷形成机制,采用光刻工艺结合化学腐蚀方法在碲锌镉衬底表面实现了网格化,研究了碲锌镉近表面富碲沉积相与外延薄膜表面缺陷的关系.结果表明:衬底近表面富碲沉积相会导致碲镉汞薄膜表面孔洞、类针形凹陷坑缺陷以及三角形凹陷坑聚集区;在液相外延过程中,高温碲镉汞熔液与CdZnTe衬底间的回熔作用可以减少与富碲沉积相相关的表面缺陷,薄膜表面缺陷与衬底表面富碲沉积相的匹配度与回熔深度负相关;回熔过程以及富碲沉积相形态、深度影响HgCdTe薄膜表面缺陷形态和分布.     

Role of a nucleation layer in suppressing interfacial pitting in

In this work, we investigate the role of a low temperature nucleation layer on the interfacial properties of InAs epilayers grown on (100) semi-insulating InP substrates using a two-step metalorganic chemical vapor deposition method. Cross-sectional and plan-view transmission electron microscopy studies were carried out on InAs films of nearly equal total film thicknesses but for different thicknesses of a nucleation layer of InAs deposited at low temperature on the substrate. Our studies show that thermal etchpits are created at the interface between the InAs film, and the InP substrate for thin nucleation layer thicknesses. This is because the low temperature nucleation layer of InAs does not cover completely the surface of the InP substrate. Hence, when the temperature is raised to deposit the bulk of the InAs film, severe thermal pitting is observed at the interface. These thermal etchpits are sources of threading dislocations. To obtain high quality InAs films and suppress interfacial pitting there is an optimum thickness of the nucleation layer. Also, our studies show that there is a relationship between the density of defects in the film and the thickness of the nucleation layer. This in turn relates to the variation of the electronic properties of the InAs films. We have observed that for all nucleation layer thicknesses, the density of threading dislocations is higher close to the interface than at the free surface of the film.     

Growth of GaN on porous SiC and GaN substrates

We have studied the growth of GaN on porous SiC and GaN substrates, employing both plasma-assisted molecular-beam epitaxy (PAMBE) and metal-organic chemical-vapor deposition (MOCVD). For growth on porous SiC, transmission electron microscopy (TEM) observations indicate that the epitaxial-GaN growth initiates primarily from surface areas between pores, and the exposed surface pores tend to extend into GaN as open tubes and trap Ga droplets. The dislocation density in the GaN layers is similar to, or slightly less than, that observed in layers grown on nonporous substrates. For the case of GaN growth on porous GaN, the overgrown layer replicates the underlying dislocation structure (although considerable dislocation reduction can occur as this overgrowth proceeds, independent of the presence of the porous layer). The GaN layers grown on a porous SiC substrate were found to be mechanically more relaxed than those grown on nonporous substrates; electron-diffraction patterns indicate that the former are free of misfit strain or are even in tension after cooling to room temperature.     

Lattice mismatch induced morphological features and strain in HgCdTe epilayers on CdZnTe substrates

HgCdTe epilayers on CdZnTe substrates can exhibit a cross-hatch pattern of periodically varying strain and surface undulations as revealed by x-ray topography, and in some cases by Nomarski optical microscopy. On { 111 } oriented material, the pattern appears as three sets of parallel lines in the 〈 110 〉 slip directions (60° apart). To investigate this phenomenon and its impact on photovoltaic device performance, we have characterized several liquid phase epitaxy (LPE)-grown HgCdTe epilayer samples by means of Lang x-ray reflection topography, synchrotron white beam x-ray topography (SWBXT), etch pit density, and other techniques. The cross hatching generally shows a correlation with the ZnTe mole fraction of the substrate. In particular, the pattern is likely to appear when the natural lattice parameter of the layer at room temperature is slightly larger or smaller than that of the substrate in the same region. We also find the corresponding pattern in { 211 } oriented layers grown by MBE. Although substantial compositional interdiffusion occurs at the layer/substrate interface during LPE growth at around 500°C, this is not a necessary condition for the cross-hatch pattern, as demonstrated by the occurrence of the pattern in MBE material grown at less than 200°C. In terms of device performance, the pattern is manifested as lines of diodes in an array having greater leakage than their neighbors. In addition to these results, we have investigated other anomalies, by means of SWBXT applied to large-area diodes that have been electrically tested. A novel technique called absorption edge contour mapping, using synchrotron white beam x-rays with a molybdenum filter, was applied to reveal the longer range lattice strain.     

Nondestructive defect characterization of SiC substrates and epilayers

This study presents a nondestructive and in-depth defect characterization method, based on the principle of polarized light microscopy (PLM), which can be used to quickly evaluate SiC substrates and epilayers. The developed PLM system has the capability to map, on a wafer scale, micropipes, elementary screw dislocations, and domain boundaries in SiC wafers. One unique feature of the PLM system is the ability to characterize the wafer with and without an epilayer, providing a newly found opportunity to investigate threading defect propagation in the overgrown epilayer. The correlation between SiC substrate defects and epilayer defects will be established.     

Chemical Vapor Deposition of Silicon Carbide Epitaxial Films and Their Defect Characterization

A chemical vapor deposition (CVD) system was designed and fabricated in our laboratory and SiC homo-epitaxial layers were grown in the CVD process using silicon tetrachloride and propane precursors with hydrogen as a carrier gas. The temperature field was generated using numerical modeling. Gas flow rates, temperature field, and the gradients are found to influence the growth rates of the epitaxial layers. Growth rates were found to increase as the temperature increased at high carrier gas flow rate, while at lower carrier gas flow rate, growth rates were observed to decrease as the temperature increased. Based on the equilibrium model, “thermodynamically controlled growth” accounts for the growth rate reduction. The grown epitaxial layers were characterized using various techniques. Reduction in the threading screw dislocation (SD) density in the epilayers was observed. Suitable models were developed for explaining the reduction in the SD density as well as the conversion of basal plane dislocations (BPDs) into threading edge dislocations (TEDs).     

Misfit relaxation behavior in CdHgTe layers grown by molecular beam epitaxy on CdZnTe substrates

Uniform layers of cadmium mercury telluride have been grown on inhomogeneous cadmium zinc telluride substrates by molecular beam epitaxy so that a single epitaxial layer experiences a laterally varying lattice mismatch. The lateral variations of layer and substrate lattice parameters, layer lattice tilt, diffraction peak width, etch pit density (EPD) and surface crosshatch have been characterized, and all measured quantities are reported as functions of the substrate lattice parameter. At small mismatch, the layer appears to be elastically deformed. Beyond a certain critical mismatch, the onset of relaxation is clearly observed in the layer lattice parameter. Relaxation leads to appearance of surface crosshatch and an increased diffraction peak width, but a reduction in EPD, suggesting a reduction in the density of threading dislocations within the layer.     

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

MOS devices built on various germanium substrates, with chemical vapor deposited (CVD) or physical vapor deposited (PVD) HfO/sub 2/ high-/spl kappa/ dielectric and TaN gate electrode, were fabricated. The electrical properties of these devices, including the capacitance equivalent thickness (CET), gate leakage current density (J/sub g/), slow trap density (D/sub st/), breakdown voltage (V/sub bd/), capacitance-voltage (C-V) frequency dispersion, and thermal stability, are investigated. The process conditions such as surface nitridation treatment, O/sub 2/ introduction in CVD process and postdeposition anneal temperature in PVD process, exhibit significant impacts on the devices' electrical properties. The devices built on germanium substrates with different dopant types and doping concentrations show remarkable variations in electrical characteristics, revealing the role of the substrate doping in the reactions occurring at the dielectric/Ge interface, which can significantly affect the interfacial layer formation and Ge updiffusion. A possible mechanism is suggested that two competing processes (oxide growth and desorption) take place at the interface, which govern the formation of the interfacial layer. Doped p-type (Ga) and n-type (Sb) impurities may enhance the different process at the interface and cause the variations in the interfacial layer formation and so on in electrical properties. The high diffusivities of impurities and Ge atoms in Ge and the induced structural defects near the substrate surface could be one possible cause for this doping effect. As another behavior of the substrate doping effect, Ge n-MOS and p-MOS stacks show quite different C-V characteristics after high temperature postmetallization anneal treatments, which can be explained by the same mechanism.     

Structure and Morphology of Inclusions in 4�� Offcut 4H-SiC Epitaxial Layers

The structure of inclusions and their influence on surface morphology, local strain, and basal plane dislocations were investigated in silicon carbide (SiC) epitaxial layers grown on 4° offcut substrates. On high-resolution x-ray topography images, strain fields were observed surrounding the inclusions. Ultraviolet photoluminescence images revealed the presence of strain-induced dislocations around the inclusions. Micro-Raman and microphotoluminescence spectroscopy showed that the inclusions exhibited a complex structure that consisted of 3C polytype regions and misoriented 4H polytype regions. The resulting lattice deformation typically propagates in the step-flow growth direction and causes distorted surface morphology.     

The relationship between lattice matching and crosshatch in liquid phase epitaxy HgCdTe on CdZnTe substrates

X-ray topography provides a very sensitive map of lattice mismatch between a HgCdTe LPE epitaxial layer and its (111) CdZnTe substrate. A well-defined Crosshatch pattern in the three «110» directions indicates a positive room-temperature lattice mismatch. For conditions of near-perfect lattice matching (±0.003% mismatch), the Crosshatch pattern disappears, presumably because there are few or no misfit dislocations present near the interface, and a region free of topographic contrast is observed. The crosshatch-free region occurs for a small positive room-temperature mismatch (about 0.02%); this is attributed to differences in the lattice matching condition at room temperature and the growth temperature. For negative mismatches, where the film is in tension, a mosaic pattern, rather than a crystallographically oriented Crosshatch, is observed in the topograph. Rocking curve full width at half maximum of the epitaxial layer is minimized in the crosshatch-free zone at a value nearly equal to that of the substrate. Etch pit density of the HgCdTe layer shows a strong minimum for perfect room temperature lattice matching, with values as low as 1 x 10⁴ cm^?2. For nearly lattice matched layers, Crosshatch is present throughout the thickness of the epitaxial layer except for a narrow graded-composition region near the substrate interface. Crosshatch contrast appears to result from long-range strain fields associated with a misfit dislocation network near the substrate interface. Spatial variations in topographic features and mismatch across relatively small lateral distances are caused by variations in substrate alloy composition. For truly lattice-matched substrates, better control over the substrate lattice parameter is required.     

Electric current controlled liquid phase epitaxy of GaAs on N+ and semi-insulating substrates

Electric current controlled liquid phase epitaxy (LPE) of GaAs has been performed on both n⁺ and semi-insulating substrates. Growth is induced by current flow across the substrate-melt interface. The furnace temperature is held constant during growth so that direct electrical control of the growth process is achieved. The dependence of the growth rate on both the electric current density across the substrate-melt interface and the ambient furnace temperature was determined. Current densities from 5 to 20 A/cm² were employed and furnace temperatures ranging from 680 to 800°C were used. Sustained steady state growth rates as small as 0.022μm/min and as large as 1.4μm/min were obtained. For a given furnace temperature and current density, the measured growth rates on semi-insulating substrates range from 48% to 77% of the rates obtained on n⁺ n substrates. The surface morphology of the epitaxial layers is observed to depend on the electric current density employed during growth. Electric current controlled doping modulation was studied in epitaxial layers grown from unintentionally doped melts. The degree of doping modulation achieved is approximately proportional to the change in applied current density. Approximately a 40% increase in the net electron concentration is obtained by changing the current density from 10 to 30 A/cm² during growth. Preliminary experiments with tin doped epitaxial layers indicate that similar changes in the amount of tin incorporation can be achieved.     

Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

GaAs/Ge heterojunction grown by metal-organic chemical vapor deposition and its application to high efficiency photovoltaic devices

We have studied the heteroepitaxial growth of GaAs on Ge substrates by metal-organic chemical vapor deposition (MOCVD). Different growth conditions and substrate orientations were employed to examine the properties of GaAs grown upon Ge substrates, and in particular the GaAs/Ge interface. The interface properties were found to strongly depend on growth conditions. By small changes in the growth temperature, the GaAs/ Ge interface was altered from active to passive. Only a narrow temperature window (600 to 630° C) for the initial GaAs layer growth gave the passive-Ge junction together with good surface morphology. Accordingly, a high efficiency (19%, AMO) GaAs solar cell was grown by atmospheric pressure MOCVD on a Ge substrate without any junction in the Ge.