Asymmetric source/drain offset structure for reduced leakage current in polycrystalline‐silicon thin‐film transistors

Abstract— An asymmetric source/drain offset structured (AOS) polycrystalline‐silicon (poly‐Si) thin‐film transistor (TFT) has ben developed by employing alternating magnetic‐field‐enhanced rapid thermal annealing (AMFERTA). The realized AOS poly‐Si TFT, with long drain‐side offset length L_Off1 and short source‐side offset length L_Off2, considerably suppresses leakage current without sacrificing ON‐current. The offset regions of the AOS TFT are naturally lightly doped due to the diffusion of n⁺ ions by AMFERTA crystallization. The fabrication process of the AOS TFT does not require any additional offset mask step or doping process. Experimental results show that the leakage current is considerably suppressed when the drain‐side offset length L_Off1 is larger than 1.25 μm.     

Fabrication of low‐temperature‐polysilicon thin‐film transistors on flexible substrates using excimer‐laser crystallization

Abstract— Low‐temperature‐polysilicon thin‐film transistors (LTPS TFTs) were fabricated on polymer substrates using sputtered amorphous‐Si (a‐Si) films and excimer‐laser crystallization. The in‐film argon concentration of a‐Si films was minimized as low as 1.6% by using an argon/helium gas mixture as the sputtering gas. By employing XeCl excimer‐laser crystallization, poly‐Si films were successfully fabricated on polymer substrates with an average grain size of 400 nm. With a four‐mask process, a poly‐Si TFT was fabricated with a fully self‐aligned top‐gate structure, and the pMOS TFT device showed a field‐effect mobility of 63.6 cm²/V‐sec, ON/OFF ratio of 10⁵, and threshold voltage of ?1.5 V.     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

Development of a 10.4‐in. UXGA display using low‐temperature poly‐Si technology

A new 10.4‐in.‐diagonal display with UXGA resolution (1600 H × 1200 V pixels) using low‐temperature polysilicon (poly‐Si) TFTs has been developed for notebook‐PC applications. The source drive technique uses integrated selector switches, which decreases the number of tape carrier packages (TCPs) for a poly‐Si TFT‐LCD and increases the connection pitch of the TCPs to the glass substrate. In this paper, we present a new display configuration and fabrication process.     

Current and future technology of low‐temperature poly‐Si TFT‐LCDs

Abstract— The state of the art of large‐area low‐temperature TFT‐LCDs will be reported in this paper. High‐performance poly‐Si TFTs are expected to realize various applications such as system display where various signal‐processing functions are added to the display. In the past few years, low‐temperature poly‐Si thin‐film‐transistor (LTPS TFT) technology has made great progress, especially in the areas of excimer laser annealing (ELA) of high‐quality poly‐Si film, ion doping for large‐area doping, and high‐quality gate SiO₂ film formation by using the low‐temperature PE‐CVD method. Also, technology trends and possible applications, such as a system displays, will be discussed.     

Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

Abstract— A complete poly‐Si thin‐film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active‐matrix displays. We present a detailed study of the poly‐Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high‐performance low‐temperature gate dielectric film. Poly‐Si grain sizes and the corresponding TFT performance have been measured for a range of excimer‐laser crystallization fluences near the full‐melt threshold, allowing optimization of the laser‐crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer‐laser pulse is described. Finally, we describe a plasma pre‐oxidation step, which has been added to a low‐temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly‐Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm² /V‐sec, threshold voltages of ?3.5 V, and off currents of approximately 1 pA per micron of gate width.     

Active‐matrix organic light‐emitting diode using inverse‐staggered poly‐Si TFTs with a center‐offset gated structure

Abstract— A low‐cost active‐matrix backplane using non‐laser polycrystalline silicon (poly‐Si) having inverse‐staggered TFTs with amorphous‐silicon (a‐Si) n⁺ contacts has been developed. The thin‐film transistors (TFTs) have a center‐offset gated structure to reduce the leakage current without scarifying the ON‐currents. The leakage current of the center‐offset TFTs at Vg = ?10 V is two orders of magnitude lower than those of the non‐offset TFTs. The center‐offset length of the TFTs was 3 μm for both the switching and driving TFTs. A 2.2‐in. QQVGA (1 60 × 1 20) active‐matrix organic light‐emitting‐diode (AMOLED) display was demonstrated using conventional 2T + 1C pixel circuits.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Flexible electrophoretic display driven by solution‐processed organic thin‐film transistors

Abstract— An organic thin‐film‐transistor (OTFT) backplane has been fabricated by using a solution‐processed organic semiconductor (OSC) and organic insulators. The OSC, a peri‐xanthenoxanthene derivative, provides a mobility of 0.5 cm²/V‐sec. These organic materials enhance the mechanical flexibility of the backplane. The developed backplane successfully drives a 13.3‐in. flexible UXGA electrophoretic display that can operate when bent at a radius of 5 mm.     

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel

Low‐temperature poly‐Si TFT data drivers for an SVGA a‐Si TFT‐LCD panel have been developed. The data drivers include shift registers, sample‐and‐hold circuits, and operational amplifiers, and drive LCD panels using a line‐at‐a‐time addressing method. To reduce the power consumption of the shift register, a dot‐clock control circuit has been developed. Using this circuit, the power consumption of the shift register has been reduced to 36% of that of conventional circuits. To cancel the offset voltage generated by the operational amplifier, an offset cancellation circuit for low‐temperature poly‐Si TFTs has been developed. This circuit is also able to avoid any unstable operation of the operational amplifier. Using this circuit, the offset voltage has been reduced to one‐third of the value without using the offset cancellation circuit. These data drivers have been connected to an LCD panel and have realized an SVGA display on a 12.1‐in. a‐Si TFT‐LCD panel.     

PECVD films for low‐temperature poly‐Si TFT‐LCD applications

Low‐temperature polycrystalline‐silicon (poly‐Si) thin‐film‐transistor (TFT) processes, based on PECVD amorphous‐silicon (a‐Si:H) precursor films and excimer‐laser crystallization, have been developed for application in the fabrication of active‐matrix liquid‐crystal‐displays (AMLCDs). The optimum process for depositing the precursor films has been identified. The relationship between excimer‐laser crystallization and poly‐Si film morphology has also been studied. Using these techniques, poly‐Si TFTs with a mobility of 275 cm²/V‐sec and on/off ratios of 1 × 10⁷ have been fabricated.     

Thermal dimensional stability of glass substrates for poly‐Si TFT‐LCD application

Abstract— Thermal dimensional stability of Fusion‐drawn Corning Code 1737 glass was investigated at simulated thermal cycles for low‐temperature poly‐Si TFT fabrication. For low‐temperature poly‐Si TFT processes between 550 and 600°C, annealed Code 1737 is required to meet a typical thermal shrinkage requirement of less than 20 ppm. For super‐low‐temperature poly‐Si TFT processes between 400 and 450°C, Code 1737 meets the requirement in the unannealed state. Code 1737 glass having a high strain point of 666°C provides thermal capabilities as a substrate for low‐temperature poly‐Si TFT‐LCD applications.     

Optimization of low‐temperature poly‐Si TFT‐LCDs and a large‐scale production line for large glass substrates

Abstract— An update of the progress of inherently low‐temperature poly‐Si (LTPS) technologies, such as ELA, ion doping, and activation in conjunction with chemical vapor deposition (CVD) and photolithography will be given. We will also discuss whether LTPS LCDs will be applied to a large‐scale production line using a large motherglass substrate. It was found that a more‐powerful excimer laser as well as photolithography with higher‐resolution and a more‐precise overlaid arrangement would enable a large‐scale production line handling motherglass of 4th generation size to be constructed in the very near future with reasonable investment and productivity costs.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

High‐performance thin‐film transistor using silicide‐mediated crystallization

Abstract— We studied the silicide‐mediated crystallization of a‐Si for low‐temperature polycrystalline‐silicon (LTPS) on glass. By controling the heating method and Ni density on the a‐Si, the grain size could be increased to 40 μm. Radial grain growth from a NiSi₂ crystalline nucleus gives rise to a large‐grain poly‐Si without amorphous phase inside. A field‐effect mobility of over 200 cm²/V‐sec was achieved by using LTPS.     

Toward sub‐micron oxide thin‐film transistors for digital holography

High‐performance 2‐μm‐channel oxide thin‐film transistors (TFT) on glass substrate for a 7‐μm‐pixel‐pitch spatial light modulator panel for digital holography applications were fabricated using a two‐step source/drain etching process. It showed a μ_FE of 45.5 cm²/Vs, SS of 0.10 V/dec, and Von of near zero voltage. Furthermore, we succeeded in the demonstration of sub‐micron TFTs, which is an indispensable route to next‐generation spatial light modulation devices with near 1‐μm pixel pitch. The issue of short‐channel transistors for display applications is also introduced. Finally, the digital holographic demonstration results based on the fabricated backplane are presented.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

A 470 × 235‐ppi poly‐Si TFT‐LCD for high‐resolution 2‐D and 3‐D autostereoscopic displays

Abstract— We have developed a 470 × 235‐ppi poly‐Si TFT‐LCD with a novel pixel arrangement, called HDDP (horizontally double‐density pixels), for high‐resolution 2‐D and 3‐D autostereoscopic displays. 3‐D image quality is especially high in a lenticular‐lens‐equipped 3‐D mode because both the horizontal and vertical resolutions are high, and because these resolutions are equal. 3‐D and 2‐D images can be displayed simultaneously in the same picture. In addition, 3‐D images can be displayed anywhere and 2‐D characters can be made to appear at different depths with perfect legibility. No switching of 2‐D/3‐D modes is necessary, and the design's thin and uncomplicated structure makes it especially suitable for mobile terminals.     

Characteristics and stability of improved re‐crystallized metal‐induced laterally crystallized polycrystalline‐silicon thin‐film transistors for display applications

Abstract— The performance of high‐temperature re‐crystallized (RC) metal‐induced laterally crystallized (MILC) polycrystalline‐silicon (poly‐Si) thin‐film transistors (TFT) have been improved by (1) patterning the active islands before MILC, (2) removing nickel‐containing residues using acid cleaning, (3) using heavily boron‐doped poly‐Si gates to achieve threshold voltage symmetry, and (4) double‐implanting n‐type source/drain junctions. A 30‐MHz driver circuit based on this improved technology was demonstrated. The reliability of optimized RC‐MILC poly‐Si TFTs has not been adversely affected by residual nickel‐containing contaminants in the TFT channel regions.