共查询到20条相似文献,搜索用时 15 毫秒
1.
DC/DC变换器的PWM控制技术 总被引:1,自引:0,他引:1
《电子产品世界》2000,(2):26-27
DC/DC变换器广泛应用于便携装置(如笔记本计算机、蜂窝电话、寻呼机、PDA等)中。它有两种类型,即线性变换器和开关变换器。开关变换器因具有效率高、灵活的正负极性和升降压方式的特点,而备受人们的青睐。开关稳压器利用无源磁性元件和电容电路元件的能量存储特性,从输入电压源获取分离的能量,暂时地把能量以磁场形式存储在电感器中,或以电场形式存储在电容器中,然后将能量转换到负载,实现DC/DC变换。开关稳压器的框图示于图1。实现能量从源到负载的变换需要复杂的控制技术。现在,大多数采用PWM(脉冲宽度调制)… 相似文献
2.
概述 近年来,随着一些高性能CPU的出现,如Pentium 4、Athlon等,需要输出电压更小,更大电流的DC/DC变换器,对热性能、EMI及负载瞬变应答(Load Transient)的要求也不断提高。传统的单相DC/DC变换器日益显示出局限性。多相DC/DC变换器以其独特的性能,为高性能CPU电源的解决方案开辟的一条新路。 相似文献
3.
Soft-switched DC/DC converter with PWM control 总被引:3,自引:0,他引:3
Oruganti R. Phua Chee Heng Guan J.T.K. Liew Ah Choy 《Power Electronics, IEEE Transactions on》1998,13(1):102-114
In this paper, a new power converter with two variations is proposed. A novel asymmetrical pulse-width-modulation (PWM) control scheme is used to control the power converter under constant switching frequency operation. The modes of operation for both variations are discussed. The DC characteristics, which can be used in the design of the power converters, are also presented. Two 50 W power converters were built to verify the characteristics of the converters. Due to the zero-voltage-switching (ZVS) operation of the switches and low device voltage and current stresses, these power converters have high full- and partial-load efficiencies. They are, therefore, potential candidates for high-efficiency high-density power supply applications 相似文献
4.
A steady-state analysis and experimental results for a dual sepic pulse-width-modulated (PWM) DC/DC power converter for both continuous and discontinuous modes of operation are presented. The converter is dual to a sepic converter, but it can also be derived from a forward converter by replacing one of its rectifier diodes with a coupling capacitor. The circuit acts as a step-down or step-up converter, depending on the value of the ON switch duty cycle. The transformerless version of the converter has a positive DC/DC voltage transfer function. Therefore, the circuit is suitable for distributed power systems. Design equations for all circuit components are derived. Experimental results measured at 100 kHz were in good agreement with theoretical predictions 相似文献
5.
6.
本文实现了一种数字控制PWM/PSM双模DC/DC Buck变换器。该变换器的两种工作模式可根据连续导通模式(CCM)或者断续导通模式(DCM)自动选择。变换器在DCM模式下工作于脉冲跨周期调制(PSM)模式,在CCM模式下工作于2MHz开关频率的脉冲调宽调制(PWM)模式。轻负载下通过跳周期工作降低了开关损耗。因此在宽负载范围内得到了较高的变换效率。文中详细阐述了PWM控制电路模块,例如模拟数字转换器(ADC),数字PWM(DPWM)和环路补偿器,以及PSM控制模块的实现。环路补偿器的参数可编程调节,以满足不同的外围器件参数以及开关频率。这一特性比模拟方式具有更大的灵活性。本文中实现的变换器采用0.13μm CMOS工艺设计并流片,芯片面积为1.21 mm2。测试结果显示变换效率在200mA负载时为90%,在20mA负载时为67%。同时,负载阶跃响应的测试结果说明了本文实现的双模变换器的良好稳定性。 相似文献
7.
A digitally controlled pulse width modulation/pulse skip modulation(PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode(DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator(DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals.The chip is manufactured in 0.13μm CMOS technology and the chip area is 1.21 mm~2.Experimental results show that the conversion efficiency is high,being 90%at 200 mA and 67%at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability. 相似文献
8.
An approximate procedure for on-line computing the loss-optimal values of the switching angles in a class of pulse width modulated converters is presented. The proposed technique is independent of the constants of the circuit and allows one to obtain a given power in the DC load with minimum loss of energy in the AC and DC filters. This corresponds to have a quasisinusoidal supply current with minimum ripple on the output load. Simulation and experimental results confirm the practical feasibility of the method 相似文献
9.
10.
11.
12.
Eun-Soo Kim Kee-Yeon Joe Moon-Ho Kye Yoon-Ho Kim Byung-Do Yoon 《Power Electronics, IEEE Transactions on》1999,14(2):258-264
An improved soft-switching topology of a full-bridge (FB) pulsewidth-modulated (PWM) DC/DC converter is described. The new topology employs an energy-recovery snubber to minimize a circulating current flowing through the transformer and switching devices. By using an energy-recovery snubber instead of adding a tapped inductor and a saturable reactor to reduce RMS current stress, the converter achieves zero-current switching (ZCS) for the right leg due to the minimized circulating current and achieves zero-voltage switching (ZVS) for the left leg due to the reflected output current during the interval of left leg transition. Both analysis and experiments are performed to verify the proposed topology by implementing a 7 kW (120 VDC, 58 A) 30 kHz insulated gate bipolar transistor (IGBT) based experimental circuit 相似文献
13.
An analytical procedure to optimize the feedforward compensation for any PWM DC/DC power converters is described. Achieving zero DC audiosusceptibility was found to be possible for the buck, buck-boost, Cuk, and SEPIC cells; for the boost converter, however, only nonoptimal compensation is feasible. Rules for the design of PWM controllers and procedures for the evaluation of the hardware-introduced errors are discussed. A PWM controller implementing the optimal feedforward compensation for buck-boost, Cuk, and SEPIC cells is described and fully experimentally characterized 相似文献
14.
Eun-Soo Kim Yoon-Ho Kim 《Industrial Electronics, IEEE Transactions on》2002,49(5):1120-1127
The conventional high-frequency phase-shifted zero-voltage-switching (ZVS) full-bridge DC/DC converter has a disadvantage, in that a circulating current flows through transformer and switching devices during the freewheeling interval. Due to this circulating current, RMS current stress, conduction losses of the transformer and switching devices are increased. To alleviate this problem, this paper proposes an improved zero-voltage zero-current switching (ZVZCS) phase-shifted full-bridge (FB) DC/DC converter with a modified energy-recovery snubber (ERS) attached at the secondary side of transformer. Also, the small signal model of the proposed ZVZCS FB DC/DC converter is derived by incorporating the effects introduced by a transformer leakage inductance and an ERS to achieve ZVZCS. Both analysis and experiment are performed to verify the proposed topology by implementing a 7-kW (120 VDC, 58 A) 30-kHz insulated-gate-bipolar-transistor-based experimental circuit. 相似文献
15.
Application of neural networks and State-space averaging to DC/DC PWM converters in sliding-mode operation 总被引:1,自引:0,他引:1
A novel output feedback neural controller is presented in This work for the implementation of sliding-mode control of dc/dc converters. The controller, which consists of a multilayer perceptron, has been trained in order to be robust for large variations of system parameters and state variables. Fast dynamic behavior is the other main advantage of the proposed controller, which allows realization of all beneficial features of the sliding-mode control technique. Other advantages of the controller are simplicity and low cost. Computer simulations have been carried out to investigate the effectiveness of the controller in voltage regulation for a relatively complex dc/dc converter topology of the Cuk converter. Simulation results confirm the excellent performance of the control system in response to large signal variations. In order to verify the simulation results, a controller prototype has been designed and built using analog components. The controller is applied to regulate the output voltage of the Cuk converter. Experimental results confirm the analytical and simulation achievements. 相似文献
16.
17.
This paper presents a new parallel three-level soft switching pulse-width modulation (PWM) converter. The proposed converter has two circuit cells operated by the interleaved PWM modulation. Thus, the ripple currents at input and output sides are reduced. Each circuit cell has two three-level zero voltage switching circuits sharing the same power switches. Therefore, the current and power rating of the secondary side components are reduced. Current double rectifier topology is selected on the secondary side to decrease output ripple current. The main advantages of the proposed converter are soft switching of power switches, low ripple current on the output side and low-voltage rating of power switches for medium-power applications. Finally, the performance of the proposed converter is verified by experiments with 1 kW prototype circuit. 相似文献
18.
Three-phase voltage- and current-source converters are the building blocks of a great number of power electronic systems. The origin of difficulties in the control of the above converters is in their nonlinear nature. In this paper, a novel modeling technique is introduced to derive the linear models of the converters from the nonlinear transformations of the conventional nonlinear models. Then, based on the derived linear models, a high-performance linear controller with satisfactory performances is designed. The bold feature of the new model is the independence of the controller design from the operating point. A DSP-based control system has been built in the lab to verify the performance of the new models and the control algorithm. The simulation and experimental results are in close agreement. The results show that the DC term and the AC-side reactive power can be controlled independently in less than one cycle. 相似文献
19.
分析了ZCS PWM DC/DC变换器电路的工作原理,探讨了主要参数的设定,并建立了基于Matlab的仿真模型,通过选择参数对仿真模型和程序进行校核和调试,证明了零电流关断电路可以有效地减小关断损耗,提高工作效率。 相似文献
20.
《Microelectronics Journal》2007,38(8-9):923-930
A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm2 is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW. 相似文献