Thermal and mechanical effects of voids within flip chip soldering in LED packages

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree.     

Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages

The work presented in this paper focuses on the behavior of anisotropically conductive film (ACF) joint under the dynamic loading of flip chip on glass (COG) and flip chip on flexible (COF) substrate packages. Impact tests were performed to investigate the key factors that affect the adhesion strength. Scanning electron microscopy (SEM) was used to evaluate the fractography characteristics of the fracture. Impact strength increased with the bonding temperature, but after a certain temperature, it decreased. Good absorption and higher degree of curing at higher bonding temperature accounts for the increase of the adhesion strength, while too high temperature causes overcuring of ACF and degradation at ACF/substrate interface––thus decreases the adhesion strength. Higher extent of air bubbles was found at the ACF/substrate interface of the sample bonded at the higher temperature. These air bubbles reduce the actual contact area and hence reduce the impact strength. Although bonding pressure was not found to influence the impact strength significantly, it is still important for a reliable electrical interconnect. The behaviors of the conductive particles during impact loading were also studied. From the fracture mode study, it was found that impact load caused fracture to propagate in the ACF/substrate interface (for COG packages), and in the ACF matrix (for COF packages). Because of weak interaction of the ACF with the glass, COG showed poor impact adhesion.     

Failure mechanism of lead-free solder joints in flip chip packages

The failure mechanisms of SnAgCu solder on Al/Ni(V)/Cu thin-film, underbump metallurgy (UBM) were investigated after multiple reflows and high-temperature storage using a ball shear test, fracture-surface analysis, and cross-sectional microstructure examination. The results were also compared with those of eutectic SnPb solder. The Al/Ni (V)/Cu thin-film UBM was found to be robust enough to resist multiple reflows and thermal aging at conditions used for normal production purposes in both SnAgCu and eutectic SnPb systems. It was found that, in the SnAgCu system, the failure mode changed with the number of reflows, relating to the consumption of the thin-film UBM because of the severe interfacial reaction between the solder and the UBM layer. After high-temperature storage, the solder joints failed inside the solder ball in a ductile manner in both SnAgCu and SnPb systems. Very fine Ag₃Sn particles were formed during multiple reflows in the SnAgCu system. They were found to be able to strengthen the bulk solder. The dispersion-strengthening effect of Ag₃Sn was lost after a short period of thermal aging, caused by the rapid coarsening of these fine particles.     

Thermal performance impacts of heat spreading lids on flip chip packages: With and without heat sinks

Heat spreading lids on a flip chip package can provide many thermal and mechanical advantages. Major drawbacks are higher module costs and potentially poorer thermal performance with a heat sink. This study compares thermal performance of direct lid attach (DLA) and bare die flip chip packages and addresses the roles of interface resistance and lid thickness. The IBM SLC^TM package is tested and modeled. JEDEC standard wind tunnel tests as well as CFD models are used for analysis. The study reveals that the DLA design without additional heat sinking can provide significantly better thermal performance compared to the bare die package, depending on package size and airflow rate. With a heat sink the performance of the lidded package can be superior or inferior depending on interface resistance, lid design and the standard used for comparison.     

Underfill of flip chip on laminates: simulation and validation

The flow characteristics of a number of underfills were evaluated with quartz dies of different patterns and pitches bonded on different substrate surfaces. Perimeter, mixed array, and full array patterns were tested. Observations on the flow front uniformity, streaking, voiding, and filler segregation were collected, The information was compared with the results predicted by a new simulation code, plastic integrated circuit encapsulation-computer aided design (PLICE-CAD) under DARPA-funded development. The two-phase model of the combined resin and air takes into account geometrical factors such as bumps and die edges, together with boundary conditions in order to track accurately the propagation of the flow fronts, The two-phase flow field is based on the volume-of-fluid (VOF) methodology embedded in a general-purpose three-dimensional (3-D) flow solver     

Effect of glue on reliability of flip chip BGA packages under thermal cycling

Glue is widely used to improve the reliability of ball grid array (BGA) under mechanical shock and vibration. Although it has been demonstrated to have a positive effect on the reliability of BGA under mechanical impact, it can have adverse effects on BGA under thermal cycling. This paper investigates the effect of glue on the reliability of BGA under thermal cycling using both experimental and numerical methods. The digital image correlation (DIC) technique was used to obtain the thermal mechanical behavior of the package. The experimental results explain in detail how the glue negatively affects the reliability of the BGA. Furthermore, a finite element analysis was performed and its results were verified with experimental results. A numerical parametric study was carried out on various mechanical properties, configurations of the glue, and introduction of a stiffener using the validated FEM model. The results show that the reliability of BGA strongly depends on geometries and material properties of the glue. Based on the results, a guideline of glue selection for BGA reliability under thermal cycling is formulated.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

Correlation of material properties to reliability performance of anisotropic conductive adhesive flip chip packages

The anisotropic conductive adhesive (ACA) is a promising solder alternative candidate that shows potential for further pitch reduction. Although much work has been published on ACA joint behavior, study on correlation of material properties with reliability performance is still lacking. The main objective in this study was to identify the impact of material properties on reliability, so as to engineer highly reliable microelectronics assemblies. Four representative ACA materials (both film and paste types) with diverse properties were selected. Material properties were characterized as close as possible to "stress test" conditions so as to allow more accurate correlation predictions. Reliability performance was obtained by assembling test chips of 200-/spl mu/m pitch onto BT-substrates, then subjecting them to reliability tests. Correlation analysis was conducted and key material properties that contributed to good reliability performance were identified. Findings indicated that the best properties for high reliability assemblies were: high adhesion strength after subjecting to "stress aging", low coefficient of moisture expansion (CME) and low elastic modulus (E).     

The optimization design of bump interconnections in flip chip packages from the electrical standpoint

Flip chip technologies have rapidly progressed and widely used in concert with the high speed and small dimension trends in electronic devices. This study performed an optimization design of the bump geometries in order to achieve higher electrical performance. The bump interconnections were considered as partial four-bump system to derive the analytical solution of the characteristic impedance. The first incident voltage determined form the characteristic impedance of the bump was employed as the optimization objective function to reduce the response time delay in the binary command for maintaining the chip level efficiency. The genetic algorithm was used for the search routines to evaluate the optimal solutions of the bump geometries in this research. Two cases of power supply voltages were adopted to conduct the case studying in both air and underfill environments. The optimization results show that a powerful design window for bump interconnections is established.     

Thermal analysis of a flip chip ceramic ball grid array (CBGA) package

The function of an electronic cooling package is to dissipate heat to ensure proper operation and reliability. The flip chip ball grid array package is probably the most suitable package for high-level thermal performance applications. A high thermal performance flip chip ceramic ball grid array (FC-CBGA) package with an aluminum silicon carbide (AlSiC) lid and one without lid were evaluated using the computational fluid dynamics (CFD) technique. This paper compares the thermal performance of a 35 × 35 mm FC-CBGA package with three different die sizes of 5 × 5 mm, 15 × 15 mm and 20 × 20 mm. The performance of a lid fitted with different heat sinks was investigated in standard JEDEC defined natural and in forced convection environments. Thermal measurements were performed using a functional application specific integrated circuit (ASIC) chip, in compliance with the JEDEC standards. Excellent agreement was found between the numerical results and the measured data. Improved thermal performance was observed with a lidded package as compared to the unlidded one. However, no significant improvement was observed between lidded and unlidded packages when fitted with a heat sink subjected to forced convection. This paper also discusses the package thermal budget estimate with and without heat sinks. Printed circuit board and package top surface temperature patterns were measured using an infrared thermal camera. The usefulness of the thermal characterization parameter is demonstrated in system level applications. Parametric studies were carried out to understand the effect of die size, radiation effect, gird size variations and airflow rate on die junction temperature and package thermal resistance. This study also incorporates the effects of substrate, lid, die and PCB temperatures for different die sizes in natural and forced convection environments.     

Study of the UBM to copper interface robustness of solder bumps in flip chip packages

Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.     

Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages

As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R-C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the global-local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep submicron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect.     

PBGA封装热可靠性分析

对PBGA封装体建立了有限元数值模拟分析模型。模型采用无铅焊点,完全焊点阵列形式。研究了封装体在经历IPC9701标准下的五种不同温度循环加载后,受到的热应力、应变,以及可能的失效形式。结果表明,焊点是封装体结构失效的关键环节,焊点所受应力大小与焊点位置有关。比较了不同温度循环下封装体的疲劳寿命。其结果为提高封装体的可靠性和优化设计提供了理论依据。     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

The effects of rheological and wetting properties on underfill filler settling and flow voids in flip chip packages

As the bump diameter and bump pitch of flip chip packages get smaller, the underfill becomes more resistant to flow. Therefore, low viscosity underfills are used in the process to increase the throughput. Problems associated with low viscosity underfills include filler settling and flow induced voids due to fast edge flow. In this paper, we will discuss how the rheological properties can affect underfill filler settling and flow voids. The effects of yield stress of underfill on filler settling and the effects of shear thickening of underfill at large shear rates on flow voids of underfill were investigated. It was shown that the underfills with small fillers have shear-thickening viscosity and yield stress. The filler settling of underfills with yield stress was greatly reduced. A video underfill flow metrology with quartz die packages was developed for flow void observation. The correlation between underfill, substrate properties, and flow voids formation based on the video underfill flow measurement will be discussed.     

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.