Evaluation of three 32-bit CMOS adders in DCVS logic for self-timedcircuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-μm two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits     

Fast adders using enhanced multiple-output domino logic

Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-μm CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path     

A comparative study on performance and reliability of 32-bit binary adders

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.     

A high-performance CMOS 32-bit parallel CRC engine

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-μm three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register     

The CMOS carry-forward adders

The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-/spl mu/m CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm/sup 2/ silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps.     

Power-delay characteristics of CMOS adders

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic design of an adder to improve its power-delay product are identified. An effective way of improving the speed of a circuit is by transistor sizing which unfortunately increases power dissipation to a large extent. It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product. Perflex, an in-house performance driven layout generator, is used to systematically generate sized layouts     

A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller

The SOC implementation of a capacitive fingerprint sensor, which embeds the 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of a 160/spl times/192 pixel array with a sensor detection circuit and the embedded 32-bit RISC microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 180% more than conventional detection circuit does and minimizes any electrostatic discharge influence by applying an effective isolation structure. The test chip was fabricated on a 0.35-/spl mu/m standard CMOS 1-poly 4-metal process.     

Power-delay product minimization in high-performance 64-bit carry-select adders

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.     

Low-power design techniques for high-performance CMOS adders

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 μm CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V     

A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-$muhbox m$standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2$muhbox m^2$three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external$hboxI^2hboxC$master device such as universal$hboxI^2hboxC$serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9$hbox mm^2$. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications.     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

32位微控制器——嵌入式市场的助推剂

下面的话听起来可能让人觉得荒谬:要进入微控制器市场,你必须事实上已经入了这一行.围绕着每一种类型的微控制器的残酷竞争已经把价格拉得如此之低,以至于如果你需要获取外设与各种存储器的许可或者购买这些构成MCU价格的主要组成部分的模块的话,你就无利可图.达还不够:你必须向你的客户提供大量的MCU结构选项.     

应用于高速CMOS图像传感器的具有动态功耗控制的12比特紧凑型列并行逐次逼近ADC

本文提出了一个应用于高速CMOS图像传感器的12比特列并行逐次逼近模数转换器。为了减小面积并使它的版图与两倍的像素间距相适应,采用了分段二进制权重开关电容数模转化器和交错结构的金属-氧化物-金属单位电容。为了消除单位电容上极板的寄生电容,提出了电场屏蔽的版图结构画法。提出了动态功耗控制技术,有效地降低了读出通道的功耗。用片外前台数字校准算法补偿开关电容数模转化器电容失配引起的非线性。芯片采用1P5M CMOS图像传感器工艺制造,其面积为20×2020μm2。采样率为833kS/s时,校准后的DNL、INL、ENOB分别为：0.9/-1 LSB、1/-1.1LSB、11.24比特。在1.8V的电源电压下,功耗为0.26 mW。随着帧率的减小,功耗线性减少。     

Optimized transmission gate-based CMOS full adders: design and analysis

By analysing the output characteristics of individual pass transistors in a transmission gate (TG) based CMOS full adder, it is possible to use fewer transistors to implement addition. Various simplified full adders with different numbers of transistors are tested using Pspice simulation. Comparison of these full adders is based on the maximum allowable offset voltages of each node in the full adder configuration. The simplest architecture with a driving output inverter only requires 14 transistors instead of the original 22, as proposed by Zhuang and Wu. Since the simplest architecture is conditional, minimizing the threshold voltage of pass transistors and a design that is more robust are desired in order to increase the fabrication yield. A 16-transistor full adder is optimized for the trade-off between area and reliability. By converting two transistors of an XOR gate into an inverter, this full adder is demonstrated to perform better than an 18-transistor full adder, especially while the inputs are degraded.     

Comparative analysis of CMOS adders circuits based on 10 transistors

Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out.     

32位MCU值得关注的技术

"32位MCU的发展趋势是要求产品所需的更高的计算性能、大容量存储、低功耗、集成的复杂性和更多的软件支持,使DSP和MCU走向功能融合(记者注:成为DSC),并有大而全的趋势."苏州国芯科技有限公司总经理肖佐楠总结道,同时,随着新型的电子设备对网络多媒体和无线功能需求的增加,MCU产品集成越来越多的模拟功能和新的外围电路.随着信息爆炸性地发展,对信息安全的需求越来越迫切,这将是MCU发展的又一新热点,因此具有集成信息安全功能的CPU和大规模数据计算处理模块设计平台将会得到MCU设计用户的欢迎.     

14-bit CMOS pipeline ADC with dual-calibration

A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 mum)     

An algorithmic 15-bit CMOS digital-to-analog converter

A digital-to-analog converter (DAC) has been designed which uses an algorithm based on interpolation. The algorithm ensures monotonicity and differential linearity despite offset voltages, and hence eliminates the need for trimming. The technique has been used to design a 15-bit DAC in a 2.5-μm CMOS technology. The converter features S/(N+THD) of 74 dB with a dynamic range of 87 dB and a power consumption of 22 mW at 44-kHz sample frequency     

A 32-bit microprocessor for Smalltalk

SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.