基于正交波形复用技术的无源光网络上行信号传输方法

提出了一种复用技术——正交波形复用(OGDM),并将其应用于无源光网络(PON)系统中作为上行信号传输。在本方法中,对于N个光网络单元(ONU)端的PON系统,先将N个ONU端信号分别通过强度调制或无载波调幅调相(CAP)技术,调制到N个两两相互正交电波形上,使"1"码对应有波形,"0"码对应无波形,然后再将各路不同的波形信号分别调制到每个ONU用户的激光器上,这些激光器的波长可以是同一个波长;通过光分配网络(ODN)单元合路后上行传输到光线路终端(OLT)端,在OLT端采用相关接收的方法,把接收到的信号和OLT端的本地正交波形作相关运算,利用正交波形的正交性来区分不同ONU端的用户信息。仿真显示在理想情况下,32路ONU信号当采用外调制方式时,每路单独占用10Gb/s,总带宽为320Gb/s,可以传输20km。     

润光泰力开发出具有1 1光纤保护和ALS功能的PDH光端机芯片

继8E1和100兆以太网混合复用芯片RC7010后,近日北京润光泰力科技发展有限公司又在此基础上推出了具有1 1光纤保护和ALS功能的PDH光端机芯片。该芯片除了实现8路E1信号和100M全速全双工以太网混合复用外;还能够提供两个光接口,内置光线路时钟和数据恢复电路(CDR),实现双光口自动     

润光泰力推出新款PDH光端机芯片具有1+1光纤保护和ALS功能

继8E1和100兆以太网混合复用芯片RC7010后,近日北京润光泰力科技发展有限公司又在此基础上推出了具有1+1光纤保护和ALS功能的PDH光端机芯片。该芯片除了实现8路E1信号和100M全速全双工以太网混合复用外;还能够提供两个光接口,内置光线路时钟和数据恢复电路(CDR),实现双光口自动保护倒换。该光接口还能提供ALS(AutomaticLaserShutdown/Reduction)功能,也可通过网管实现用户定义ALS功能。总的来讲,RC7017是一颗功能强大的系统芯片,既适合于直接实现普通光端机产品,又提供了丰富的扩展功能,用于开发个性化的、具有自己公司特色的光…     

基于光FFT的8×112Gbit/s全光OFDM光纤传输系统

采用单个激光源,通过差分马赫-曾德尔(M-Z)外 调制器产生8根等频率间隔为28GHz的光频梳,每根 光频梳彼此相干并作为光子载波,经112Gb/s偏分复用(PDM)-正交 相移键控(QPSK)信号调制后,波分复用后形成8路宽带的全光正交频分复用( OFDM)信号。接收端通过基于级联M-Z延时干涉仪(MZDI)的光学快速傅里叶变换(OFFT)实现 全光OFDM信号的解复用。 解复用后的每路信号经光采样后,采用与单载波PDM-QPSK系统中相同的数字相干解调进行 数据恢复。提出的8×112Gb/s全光OFDM系统在背靠背情况下,误码 率(BE R)为10－3时,光信噪比(OSNR)较单 载波112Gb/s PDM-QPSK系统多约9dB。8×112Gb/s全光OFDM信号经480km光纤传输后, OSNR损伤约1.6dB。仿真结果表明,全光 OFDM系统的数字相干接收机可以较容易地实现对现有单载波系统扩容,并且不影响系统的传 输性能。     

基于小波包变换码的新型无源光网络上行信号复用和传输方法

提出了一种基于小波包变换正交码的多电平正交编码的无源光网络(PON)中上行信号复用和传输新方法,将PON系统中各个不同的光网络单元(ONU)用户用小波变换正交码来进行调制、复用和传输,能够实现各个不同ONU用户共享一个波长。由于采用了小波变换编码,可以实现数量很多ONU用户同时上行,在ONU端不需要突发光模块以及多波长激光器,因而成本低,传输速率高,接入数量多。给出了基于该方法的上行系统调制、复用和传输的结构模型,并仿真了传输速率为1.25Gb/s和10Gb/s下不同路ONU用户上行传输,仿真结果表明,最大可以实现上行32路,每路10Gb/s,总传输速率达到320Gb/s的高速PON系统。     

EPON中纯数据型ONU的设计方案与简单测试

一个典型的EPON (以太网无源光网络)系统由OLT(光线路终端)、POS(无源光纤分支器)、ONU(光网络单元)组成。ONU处于EPON系统中的用户端,主要在OLT的控制下,完成相应的功能。它通过TDMA(时分复用)方式进行数据的上行传输、突发发送和数据接收。ONU根据扩展用户端口的不同,可划分为纯数据型、数据加语音型和三网合一型。本文介绍了EPON中纯数据型ONU的系统组成,并通过实例说明了其设计方案和在未与OLT对接的情况下如何进行简单的测试。     

润光泰力推出PDH光端机芯片

(本刊讯)继8E1和100兆以太网混合复用芯片RC7010后,近日北京润光泰力科技发展有限公司又在此基础上推出了具有1 1光纤保护和ALS功能的PDH光端机芯片。该芯片除了实现8路E1信号和100兆全速全双工以太网混合复用外,还能够提供两个光接口,内置光线路时钟和数据恢复电路CDR,实现双光口自动保护倒换。该光接口还能提供ALS功能,也可通过网管实现用户定义ALS功能。总的来讲RC7017是一颗功能强大的系统芯片,既适合于直接实现普通光端机产品,又提供了丰富的扩展功能,用于开发个性化的、具有自己公司特色的光端机设备。润光泰力推出PDH光端…     

EPON ONU芯片的硬件验证与测试平台设计

介绍了SHU 2006 ONU芯片的硬件验证与测试平台系统,利用该验证平台实现了SHU 2006 ONU芯片的功能以及TBI高速接口的时序测试.在该验证平台上,100M以太网的FTP数据传输速率可以达到8Mb/s.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

基于加权表决的POF信号时钟数据恢复方法

针对POF数据传输特点,提出了一种基于加权表决的全数字时钟数据恢复(CDR)方法.引入数据窗口,消除了传统数字CDR电路中存在的恢复时钟1/N UI峰峰抖动,运用加权表决恢复数据,增强了电路抗干扰能力.该方法基于FPGA通过单PLL实现了100Mb/s的POF数据传输.仿真和实验测试结果表明,该方法可快速同步相位变化,电路输入抖动容限可达0.28UI.     

Multifunctional characteristics of 1.5-/spl mu/m two-section amplifier-modulator-detector SOA

The multifunctional characterization of a two-section amplifier-modulator-detector semiconductor optical amplifier (AMD-SOA) is presented. Detectivity is analyzed in terms of bandwidth and responsivity while modulation properties are characterized by temporal response and extinction ratio. Receiver sensitivities of -26 dBm at 155 Mb/s and -19.5 dBm at 622 Mb/s and error-free signal modulation/transmission with simultaneous 10 dB amplification at 622 Mb/s with a 2/sup 23/-1 PRBS signal are reported. This device could find application as transparent add-drop node in photonic packet-switched optical ring networks.     

光纤数字通信系统5B6B编译码的FPGA实现

介绍了5B6B编译码原理,并在改进的5B6B码的基础上设计了5B6B编译码电路,实现了12条E1电路和1条100M线速以太网数据通道的混合复用。对设计数字光端机具有一定的参考作用。     

Si基单片集成850nm光接收芯片研究

设计并制备了一种Si基单片集成850nm光接收芯片,包括"P+/N-EPI/BN+"结构的光电探测器(PD)、跨阻前置放大电路及其后续处理电路。分析了PD的结构,并对其光谱响应及频率响应进行模拟,在2.0V偏压下,PD在850nm的响应度为0.131A/W,截止频率为400 MHz。采用0.5μm BCD(bipolar、CMOS和DMOS)工艺流片,光接收芯片面积约为900μm×1 100μm。测试结果表明,PD暗电流为pA量级,响应度为0.12A/W。光接收芯片在155 Mb/s速率及误码率(BER)小于10-9情况下,灵敏度为-12.0dBm;在622 Mb/s速率及BER小于10-9情况下,灵敏度为-10.0dBm,并能得到清晰的眼图。将该光接收芯片封装后接入光接收模块,进行点对点光互联实验,获得很好的光信号通路。     

Digital Coherent Receiver for Phase-Modulated Radio-Over-Fiber Optical Links

A novel digital signal processing-based coherent receiver for phase-modulated radio-over-fiber (RoF) optical links is presented and demonstrated experimentally. Error-free demodulation of 50-Mbaud binary phase-shift keying (BPSK) and quadrature phase-shift keying data signal modulated on a 5-GHz radio-frequency (RF) carrier is experimentally demonstrated using the proposed digital coherent receiver. Additionally, a wavelength- division-multiplexing (WDM) phase-modulated RoF optical link is experimentally demonstrated. A 3$, times ,$50 Mb/s WDM transmission of a BPSK modulated 5-GHz RF carrier is achieved over 25 km for the WDM channel spacing of 12.5 and 25 GHz, respectively.      

PDH到622Mb/sSDH/SONET映射芯片实现

 设计了PDH到622 Mb/s SDH/SONET的映射及逆映射芯片.集成了DS1/E1/J1成帧器、DS1/DS3复接电路和E1/E3复接电路,具有622 Mb/s和155 Mb/s的高速标准接口和3通道STM-1/STS-3分插复用总线接口,支持复用段1+1保护和UPSR环形网络拓扑结构.单片实现84通道DS1/J1或63通道E1到STM-1/STS-3的映射复用功能及多通道DS3/E3/STS-1到STM-4/STS-12的映射复用功能.支持点对点应用和环形应用,交换模式支持2016通道DS0/E0的应用.4颗芯片实现336通道DS1/J1或252通道E1到STM-4/STS-12的映射复用功能.采用TSMC 0.13 μm CMOS工艺流片,芯片规模约600万门,700管脚 PGBA封装,满足光纤通信传输的要求,并成功用于光纤通信设备.     

北斗B1C信号及导航电文的特点分析与比较

我国北斗全球卫星导航系统工程建设已经启动,北斗互操作信号B1C的接口控制文件已经发布。本文重点对北斗B1C信号及导航电文进行介绍,并对其信号及导航电文的设计特点进行分析,同时与GPS L1C和Galileo E1OS互操作信号进行比较。分析显示,北斗B1C的信号和导航电文编排,在充分借鉴GPS L1C和Galileo E1OS信号特点的基础上,进行了优化设计。B1C信号具有与L1C信号和E1OS信号相同的中心频点和频谱结构,采用了数据导频支路、MBOC调制、分层码结构等设计方案,导航电文与GPS L1C也较为相近,实现与GPS L1C、Galileo E1OS信号的互操作。同时B1C也具有自身独有特点,如B1C导频支路采用QMBOC(6,1,4/33)调制方式、导航电文采用64进制LDPC编码,在实现互操作的基础上,也创新了自身特色。相对于北斗B1I信号,北斗B1C信号具有更好的弱信号跟踪、更短的首次定位时间等服务性能。     

A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/sLED-driver for low cost optical fiber links

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 μm digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 kΩ), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 μA input modulation currents. This results in a transimpedance bandwidth of 18 THzΩ, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems     

Optically-cascaded, multistage switching operation of a multifunctional binary optical/optoelectronic switch

Optically cascadable and multifunctional binary optical switches consisting of AlGaAs-GaAs vertical cavity surface-emitting lasers (VCSELs), heterojunction bipolar transistors (HBTs), and p-i-n photodetectors (PINs) have been realized. Each switching element consists of a pair of PIN/HBT/VCSEL switches that can perform optical switching and routing at a data rate of 100 Mb/s, and optoelectronic signal conversion at a data rate of 100 Mb/s, while achieving a peak dc optical gain of 18 and an ac optical gain of 4. Optically-cascaded, multistage switching operation has been demonstrated using two linear arrays of HBT/PIN/VCSEL switches, with an overall cascaded dc optical gain of 50 and an ac gain of 8.     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

A SONET STS-3c user network interface integrated circuit

Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s