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为了提高AES的加密效率,在分析影响AES多引擎并行处理的相关因素的基础上,提出了AES多引擎并行处理架构,并分析了基于ECB工作模式下的数据分配调度机制.通过对AES密码算法的逻辑综合和多密码处理引擎的参数定量分析表明,在100MHz的核心频率下,对128比特长度的密钥,4个AES密码处理引擎并行处理的数据吞吐率可以达到4.98Gb/s. 相似文献
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针对高级加密标准(Advanced Encryption Standard,AES)算法需要兼容不同工作模式以及不同密钥长度的加密需求,提出全通用AES加密算法。该算法通过设计可调节密钥扩展模块和模式选择模块,实现128/192/256位宽的加密,支持ECB/CBC/CFB/OFB/CTR 5种工作模式。基于Xilinx公司的XC7VX690T FPGA综合仿真,资源消耗为1 947 Slices,最高工作频率为348.191 MHz。 相似文献
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由于对广泛使用的AES算法的性能要求越来越高,基于软件的密码算法已经越来越难以满足高吞吐量密码破解的需求,因此越来越多的算法利用现场可编程逻辑门阵列(FPGA)平台进行加速。针对AES算法在FPGA硬件上存在的开发复杂度高且开发周期长等问题,采用高层次综合(HLS)设计方法,使用高级程序语言描述并设计AES硬件加速算法。首先利用循环展开等提高运算并行度;其次使用资源平衡技术进行优化,充分利用片上存储和电路资源;最后添加全流水结构,提高整体设计的时钟频率和吞吐量,同时也详细对比分析基准设计、利用结构展开、资源均衡以及流水线优化方法的设计。经过实验表明,在Xilinx xc7z020clg484 FPGA芯片上,最终AES算法的时钟频率最高达到127.06 MHz,而吞吐量达到了16.26 Gb/s,较之基准的AES设计,性能提升了三个数量级。 相似文献
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Authenticated encryption schemes provide both confidentiality and integrity services, simultaneously. CAESAR competition will identify a portfolio of authenticated ciphers, which is expected to be suitable for widespread adoption and offers advantages over AES-GCM. An important criterion for selecting the final candidates, besides security, is the hardware performance in resource-limited environments. In this paper, SILC, CLOC, AES-JAMBU, and COLM authenticated ciphers have been selected from the third round of the CAESAR competition for hardware evaluation. The main reasons to choose these schemes are their lightweight design, sufficient security level, and the use of the AES algorithm as their underlying block cipher. To the best our knowledge, it is the first time that an 8-bit lightweight architecture which is compatible with API v2 is presented for the selected schemes. To implement AES, the Atomic-AES v2 which is one of the smallest implementations has been adopted according to the requirements of the selected schemes. Furthermore, to reduce the area in the hardware implementation, several techniques are used, including implementing one AES core in the datapath, sharing registers to store intermediate values, implementing the tweak functions with the shuffling of wires, and implementing doubling on the GF(2128) with 8-bit architecture to construct the higher-order multipliers. The implementation results are presented on ASIC and FPGA platforms. The proposed architecture for each scheme on the two platforms is similar, but different optimization techniques are used for each platform, e.g. the AES S-box is implemented as ROM-based and logic-based on FPGA and ASIC, respectively. The comparing of the results with 128-bit implementations shows that the area on FPGA and ASIC is reduced up to 65% and 88%, respectively. The results of the current study demonstrate that AES-JAMBU has the lowest hardware area and the highest throughput and performance on both platforms. Besides, CLOC has the highest area reduction on both platforms, compared with those of the 128-bit implementations. 相似文献
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提出一种超低成本的先进密码算法(AES)的VLSI实现方案.为了尽量减小硬件开销,将每轮128位的加解密运算分成4次32位运算,以两级流水线结构实现,同时通过模块复用和优化运算次序,特别是提出了一种低成本的密钥扩展结构,以很小的硬件代价获得很高的性能.本设计采用HHNEC 0.25um标准CMOS工艺,单元面积仅约12k等效门;在100MHz工作频率下,128位加密的数据吞吐率达到256Mbps. 相似文献
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Rong‐Jian Chen Jun‐Jian Lin Su‐Min Hung Jui‐Lin Lai Shi‐Jinn Horng 《Concurrency and Computation》2011,23(12):1332-1347
This paper presents the architecture design of a high‐efficient and non‐memory Advanced Encryption Standard (AES) crypto‐core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (28) to Galois Field GF(((22)2)2) can significantly reduce the hardware complexity of the SubBytes Transformation (S‐box). Besides, the on‐the‐fly key expansion function is used to replace the RAM‐based, and the new on‐the‐fly key scheduler fully supports AES‐128, AES‐192 and AES‐256. Moreover, resource‐sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. FPGA experiment results show that the AES core works at 175.75 MHz clock. It takes about 33 clocks and 66 clocks to complete an AES‐128 encryption and decryption, respectively. That is, the corresponding throughputs are 681.7 and 340.85 Mbps. The hardware cost of the AES design is about 2420 slices with 3‐in‐1 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN chips due to its acceptable power dissipation. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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AES在安全性、高性能、高效率、易用性和灵活性等方面都具有显著的优点,随着业界对计算性能要求的不断提高,在FPGA上实现AES加解密硬核的研究得到了越来越多的关注。在深入分析AES算法的基础上,提出了基于FPGA的AES全流水硬件核设计模型。模型中改进了ae数据块和轮运算的硬件设计结构,有效地提高了AES硬核的计算性能。在Altera公司EP4CE40F23C6FPGA上的硬件实现结果显示,该AES硬核的硬件资源消耗为6413个LE和80个M9K,工作频率为310MHz,计算吞吐率为9.92Gbps,获得了非常好的计算加速效果。 相似文献
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Vanitha Mohanraj R. Sakthivel Anand Paul Seungmin Rho 《International journal of parallel programming》2018,46(5):904-922
Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and confidentiality. AES algorithm helps to provide data confidentiality while authentication is provided by a universal GHASH function. Since most of existing GCM architectures concentrated on power and area reduction but an compact and efficient hardware architecture should also be considered. In this paper, high-performance architecture for GCM is proposed and its implementation is described. In order to achieve higher operating frequency and throughput, pipelined S-boxes are used in AES algorithm. For a GCM realization of AES, a high-speed, high-throughput, parallel architecture is proposed. Experimental results proves that the performance of the proposed work is around 17% higher than the existing architecture with 3 Gb/s throughput using TSMC 45-nm CMOS technology. 相似文献
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为探究现场可编程门阵列(FPGA)密码芯片运行时电磁辐射造成的涉密信息泄漏情况,研究了互补金属氧化物半导体(CMOS)电路直接电磁辐射的原理,构建了FPGA密码芯片的近场电磁辐射模型。根据这个模型,探讨了近场电磁辐射测量点的选取,采用电磁扫描的方法解决了电磁探头在FPGA表面电磁信号采集的定位问题。此外,在阐释了差分电磁分析(DEMA)攻击原理的同时,完成了高级加密标准(AES)的FPGA电路设计,针对FPGA密码系统的DEMA攻击实验表明,通过电磁扫描找到最佳测量点,在42 000个样本的条件下能成功破解AES密码电路的128 bit密钥。 相似文献
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针对可重构阵列处理器访存数据量大、数据并行性要求高且数据全局重用少、局部性明显的特点,提出了一种分布式Cache结构的簇内局部优先高效互连访问结构,该结构实现了簇内4×4个PE对4×4个Cache的并行访问,选用Xilinx公司的ZYNQ系列芯片XC7Z045 FFG900-2进行FPGA综合。在无冲突情况下,该互连结构支持簇内16个PE的同时读/写访问,最高频率可达221 MHz,访存峰值带宽为7.6 GB/s。在此结构上实现了灰度共生矩阵提取纹理图像特征算法,数据访存带宽达到478.125 MB/s,运行时间为0.24 ms。 相似文献
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STREAM是微处理器上内存性能的基准测试程序,在多核多线程FT1000微处理器上发挥高性能是具有挑战性的研究工作。基于多级Cache结构,优化STREAM四个程序的指令流水线,根据寄存器数,设计了多级循环展开方法,根据指令延迟和Cache行的大小确定数据预取的数目,使用汇编语言编写了优化子程序。基于OpenMP并行环境,设计了STREAM并行程序,优化了局部化数据分配方式。数据测试结果表明,优化后的STREAM的性能比原始串行程序性能提高了19.2%~64.2%。优化后,并行程序的最高访存性能达到8.5 GB/s,对比优化前的最高访存性能最大提高了22.7%。 相似文献