Scaled dielectric antifuse structure for field-programmable gatearray applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×10¹² s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N⁺ antifuse structures     

A sublithographic antifuse structure for field-programmable gatearray applications

The authors demonstrate an antifuse structure with a cell area of 0.2×0.2 μm² which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2-μm lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse     

Vertical p-i-n polysilicon diode with antifuse for stackable field-programmable ROM

A field-programmable, stackable memory cell using 0.15-/spl mu/m technology is demonstrated. Vertical polycrystalline silicon diodes are stacked on top of one another, with tungsten (with TiN adhesion film) interconnect wires. An SiO/sub 2/ antifuse film separates the top of each diode from the TiN-W films. The cell is programmed when sufficient biasing voltage is applied to break down the antifuse, connecting the diode to tungsten. The cell is unprogrammed when the antifuse is intact. Cell fabrication and performance are described.     

EPROM high-speed erasing scheme

We report a technique for erasing an EPROM using the output from a Cu II laser at 2600 Å. By focusing the laser output on a portion of the chip, reliable erasure of a selected number of memory locations is obtained with an exposure time of approximately 35 ms. With the entire chip illuminated by the unfocused laser output, all memory locations are erased after an exposure time of several seconds. This method affords both high-speed and selective erasure of EPROM memory locations.     

An architecture for a DSP field-programmable gate array

This paper describes an application specific architecture for field-programmable gate arrays (FPGAs). Emphasis is placed on the logic module architecture and channel segmentation for the FPGAs targeted for application areas related to digital signal processing (DSP). The proposed logic module architecture is well-suited for efficient implementation of frequently used logic functions in the DSP application area. This is mainly because it is possible to implement most of these functions using one logic module, which results in a reduction in both the net lengths and the number of antifuses used. The performance improvements are achieved by customizing the logic module architecture and the programmable interconnect to suit the requirements of DSP applications     

A post-package bit-repair scheme using static latches withbipolar-voltage programmable antifuse circuit for high-densityDRAMs

A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of V_CC and -V_CC, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-μm triple-well 256-M SDRAM     

An erase model for FAMOS EPROM devices

A physical model is presented which explains the various features of the UV erase process in FAMOS EPROM devices. An erase sensitivity factor is defined in this model, and correlated with experimental results. The erase sensitivity factor was found to be proportional to the floating-gate photoinjecting area, and inversely proportional to oxide thickness and total capacitance of the floating gate. Photoinjection of electrons from thin strips on the floating-gate edges are shown to be responsible for the charge removal from the floating gate. Quantum yields in the order of 10^-4were measured for this erase process and correlated with values found in the literature. In addition, theI-Vand spectral characteristics of photoinjected currents as low as 10^-15A from poly-Si to SiO2in FAMOS devices were measured and compared to data from Si-SiO2structures. Special features pertaining to the erase of a fully covered floating-gate FAMOS cell were investigated: the decrease in erase rate at lowDelta V_{t}is discussed, as well as the optical access to the floating gate in these devices. Based on experimental and theoretical grounds, hole injection is discounted as a possible erase mechanism in the structures investigated.     

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.     

A novel productivity-driven logic element for field-programmable devices

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.     

High-performance metal/silicide antifuse [for CMOS technology]

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Ω, which is a factor of 10 less than that of Si-based antifuses (poly/n⁺ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory     

Configurable analogue building blocks for field-programmable analogue arrays

In this article, the design of configurable analogue blocks for field programmable analogue arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. The realisation of these functions depends on differential continuous-time current-mode translinear loop techniques. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by modifying the block's biasing conditions digitally. Simulation results for the presented circuits are included.     

A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme

This paper represents the low-power signal-delta (ΣΔ) modulator for wireless communication receiver applications. The 2nd-order modulator has a single-loop structure with 11 quantization levels. An adaptive biasing scheme of the operational amplifier and cascaded comparator scheme are proposed in order to save the power consumption. The DAC with three-level references including the analog ground voltage can make the modulator be implemented with half of the input capacitances without degradation of linearity characteristics with the help of dynamic element matching technique. Peak SNR values of 74 dB and 68 dB are achieved with the input bandwidths of 615 kHz and 1.92 MHz for CDMA-2000 and WCDMA applications, respectively. The modulator is fabricated in a 0.13-μm standard digital CMOS technology and dissipates 4.3 mA for a single supply voltage of 2.8 V. Jinup Lim was born in Seoul, Korea, in 1973. He received the B.S. and the M.S. degrees in semiconductor engineering from University of Seoul, Seoul, Korea, in 1999 and 2001, respectively. From 2001 to 2002, he worked in GCT Semiconductor Inc., Seoul, Korea. He is currently working toward the Ph.D. degree in Electrical & Computer Engineering at the same university. He received the Best student paper award from IEEE SSCS/EDS Seoul Chapter in 2004 and the Samsung Best paper award third prize in ISOCC 2004. His research area is the design of high-performance discrete-time / continuous-time sigma-delta modulator circuits. Joongho Choi was born in Seoul, Korea, in 1964. He received the B.S. and the M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1987 and 1989, respectively. In 1993, he received Ph.D. degree in electrical engineering from University of Southern California, CA, USA. From 1994 to 1996, he worked in IBM T. J. Watson Research Center, NY, USA. In 1996, he joined the University of Seoul, Seoul, where he is currently a professor in the Department of Electrical & Computer Engineering. His research area is the design of high-performance analog integrated circuits.     

VIPMOS-a novel buried injector structure for EPROM applications

A buried injector is proposed as a source of electrons for substrate hot electrons injection. To enhance the compatibility with VLSI processing, the buried injector is formed by the local overlap of the n-well and p-well of a retrograde twin-well CMOS process. The injector is activated by means of punchthrough. This mechanism allows the realization of a selective injector without increasing the latchup susceptibility. The p-well profile controls the punchthrough voltage. The high injection probability and efficient electron supply mechanism lead to oxide current densities up to 1.0 Å.×cm^-2. Programming times of 10 μs have been measured on nonoptimized cells. The realization of a structure for 5-V-only digital and analog applications is viable. A model of the structure for implementation in a circuit simulator, such as SPICE, is presented     

An enhanced erase mechanism during channel Fowler-Nordheimtunneling in flash EPROM memory devices

An enhanced erase behaviour observed during the channel Fowler-Nordheim (FN) tunneling erase operation was examined in details. This enhanced erase occurs when a high p-well voltage is used, with the source and drain junctions of the cell left floating, during the erase operation. Our investigation indicates that the floating source and drain take on a high junction voltage during the p-well voltage transient. This causes transient band-to-band tunneling, and in some cases, junction avalanche breakdown, to occur in the source and drain junctions. As a result, hot-hole injection into the floating gate takes place to create this enhanced erase phenomenon     

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Specific applications require large amounts of high-performance, dense and low-cost non-volatile memories with CMOS standard process compatibility. There exists numerous structures for one-time-programming (OTP) bitcells, exploiting various physical phenomena as programming modes. Not all of these physical phenomena will behave in a satisfactory manner with the CMOS technology shrink. Moreover, it is not easy to evaluate the effect of geometry and technology on the trade-off between density and reliability of the OTP bitcells.This paper aims to review literature about OTP memories and show that metal fuse, polyfuse and antifuse are the best candidates so far. Other memories require either additional masks with regards to core process, additional technological steps or unaffordable programming conditions. Significant results will be listed in comparison tables.This paper also wishes to give a summary of the physical phenomena involved in bitcell architectures. Opinions are given about the suitability of OTP architectures for specific applications, the most suitable bitcell architectures have been layouted in 65 and 45 nm for density comparison purpose. Particularly, promising structures are manufactured and characterized as they present fair trade offs for standard CMOS process. Discussion and conclusion are intended to give a comprehensive review about the parameters impacting the performances, the density and the cost of the OTP bitcell. Comparison tables are edited with the most pertinent parameters and available results.     

Survey of circuitry for wristwatches

Circuit requirements, as well as practical realizations, are discussed for different types of electronic wristwatches, namely, the spring-balance, tuning-fork, and quartz-crystal-controlled movements. Particular emphasis is placed on the oscillator, frequency divider, and motor-drive circuits for quartz watches. Bipolar integrated circuits are well adapted for oscillators and motor-drive circuits producing high current pulses (1 mA). Bipolar frequency dividers with adequate power consumption are possible up to approximately 32 kHz. Complementary MOS circuits offer the important advantages of low consumption and high density of integration. This technology presently appears to be a good solution for advanced watch designs using higher frequency quartz and electronic display systems. The discussion includes a general view of the evolution in this area. For this purpose references are given.     

基于反熔丝结构的低成本嵌入式一次可编程4-kbit 存储器宏

A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.     

An enhanced entropy coding scheme for HEVC

This paper presents a modification to Context-based Adaptive Binary Arithmetic Coding (CABAC) in High Efficiency Video Coding (HEVC), which includes an improved context modeling for transform coefficient levels and a binary arithmetic coding (BAC) engine with low memory requirement. In the improved context modeling for transform coefficient levels, the context model index for significance map is dependent on the number of the significant neighbors covered by a local template and its position within transform block (TB). To limit the total number of context models for significance map, TBs are split into different regions based on the coefficient position. The same region in different TBs shares the same context model set. For the first and second bins of the truncated unary scheme of absolute level minus one, their context model indices depend on the neighbors covered by a local template of the current transform coefficient level. Specifically, the context model index for the first bin is determined by the number of neighbors covered by the local template with absolute magnitude equal to 1 and larger than 1; for the second bin, its context model index is determined by the number of neighbors covered by the local template with absolute magnitude larger than 1 and larger than 2. Moreover, TB is also split into different regions to incorporate the coefficient position in the context modeling of the first bin in luma component. In the BAC engine with low memory requirement, the probability is estimated based on a multi-parameter probability update mechanism, in which the probability is updated with two different adaption speeds and use the average as the estimated probability for the next symbol. Moreover, a multiplication with low bit capacities is used in the coding interval subdivision to substitute the large look-up table to reduce its memory consumption. According to the experiments conducted on HM14.0 under HEVC main profile, the improved context modeling for transform coefficient levels achieves 0.8%, 0.6% and 0.4% bitrate reduction on average for all intra (AI), random access (RA) and low delay (LD) configurations, respectively; the BAC engine with low memory requirement achieves 0.7%, 0.6% and 0.5% bitrate reduction on average for AI, RA and LD configurations, respectively; the overall bitrate reduction achieved by the proposed two techniques is 1.4%, 1.1% and 0.9% on average for AI, RA and LD configurations, respectively.     

An efficient receiver scheme for downlink ZP-CDMA

A signal transmitted through a wireless channel may be severely distorted by intersymbol interference (ISI) and multiple access interference (MAI). In this paper, we propose an efficient CDMA receiver based on frequency domain equalization (FDE) with a regularized zero forcing (RZF) equalizer and parallel interference cancellation with a unit clipper decision function (CPIC) to combat both the ISI and the MAI. We call this receiver the FDE-RZF-CPIC receiver. This receiver is suitable for downlink zero padding CDMA cellular systems. The effects of the decision function, the channel estimation, the number of cancelled users, and the user loading on the performance of the proposed receiver are discussed in the paper. The bit error rate (BER) of the data received by the proposed receiver is evaluated by computer simulations. The experimental results show that the proposed receiver provides a good performance, even with a large number of interfering users. At a BER of 10^?3, the performance gain of the proposed receiver is about 2 dB over the RAKE receiver with a clipper decision function and PIC in the half-loaded case (eight users) and is much larger in the full-loaded case (16 users).