Optimum cyclic redundancy codes for noisy channels (Corresp.)

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16-bit ADCCPt polynomial is designed for digital links that already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of the resulting digital circuit may be much lower. This leads to the consideration of 3-byte (24-bit) and 4-byte (32-bit) polynomials. Generator polynomials of a certain class are found that have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular polynomials for 24-bit and 32-bit redundancies are exhibited, of weight and distance 6 in the 24-bit case and weight 10 and distance 8 in the 32-bit case.     

Reliability-based incremental redundancy with convolutional codes

Incremental redundancy, or Hybrid type-II ARQ (HARQ), algorithms use a combination of forward error correction and retransmissions to guarantee reliable packet data communications. In this work, we propose a HARQ algorithm that exploits received packet reliability to improve system performance. Specifically, the receiver uses the average magnitude of the log-likelihood ratios of the information bits as the packet reliability metric, which is then used to determine the sizes of subsequent retransmissions. The proposed retransmission strategy attempts to maximize user throughput while satisfying a maximum packet delay constraint. The performance of our reliability-based HARQ algorithm is evaluated in static and time-varying channels through simulations. Furthermore, analytical results on the relationship between the reliability metric, the code rate and the block error rate are presented.     

基于循环冗余校验的极化码研究

极化码具有简单明确的编码方式和译码算法,在理论上被证明可以达到香农极限。但是其连续删除译码(SC译码)始终在单路径上逐比特进行译码,导致其实际译码性能并不理想。连续删除列表译码(SCL译码)是SC译码的改进型算法,这种译码方式以付出一定译码复杂度为代价提高了极化码的译码性能。而将SCL译码结合循环冗余校验(CRC)可以译码多路径中错误译码的概率,基于这一点该文将对不同CRC码结合极化码所产生的性能差异进行分析,从而得到合适的CRC     

性能改进的16位超前进位加法器

加法运算是最重要最基本的运算,所有的其他基本算术运算,减、乘、除、模乘运算最终都能归结为加法运算。在不同的场合使用的加法器对其要求也不同,有的要求速度更快,有的要求面积更小。基于速度更快的要求,对3种常用加法器从结构与性能上进行比较,给出了综合面积与速度的比较。进而对超前进位加法器进行了进一步改进,加入了流水线结构设计,大大提高了其速度性能。     

16位MCU攻略——是否是8位和32位之间的灰色地带?

16位单片机(微控制器,MCU)一向是一个颇有争议的产品地带:往高走有32位MCU一大批厂商及其丰富的产品线顶着,向下游更有五花八门的8位单片机世界窥视着.因此,四、五年前,业内流行着这样一种看法:16位单片机是8位与32位微控制器之间的灰色地带,除了汽车等利基市场外,少有发展机会了.几年过去了,16位单片机市场到底如何?     

MD16:基于特定RISC规则的16位DSP处理器

为达到最佳的应用性价比,一个重要思想就是把RISC和DSP的优点融合在一个平台上,但是目前这方面工作侧重以RISC结构为基础构建RISC-DSP混合型处理器。与此对比,本文提出了一种以DSP为基础并辅以若干RISC特性的处理器构造思想。这种思想表现在体系结构设计上为采用局部类RISC同质寄存器结构来优化指令编码、采用基于二维扩展LAOD/STORE寻址机制来增强寻址能力;表现在微结构设计上为采用类RISC四级流水线来降低控制、数据相关性,同时由于基于寄存器的运算操作和扩展的LOAD/STORE寻址操作功能正交,因此又可采用指令内并行机制来提高运行效率。芯片采用SMIC 0.18μm6层CMOS工艺加工,在核心电压1.8V情况下,其可工作在0～162MHz,此时功耗为1.1mW/MHz。     

A 16-bit self-testing multiplier

A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.     

A 16-bit LSI minicomputer

A 16-bit LSI minicomputer, using n-channel MOS technology, has been developed. The instruction set contains 126 instructions including floating-point arithmetic and is fully compatible with commercially available minicomputers such as the TOSBAC-40 and the Interdata 70. An execution speed of 2 /spl mu/s is obtained for register to register (RR) instructions. All the central processing unit (CPU) functions are implemented on a single board. An external microprogram ROM and short-single address microinstructions are used to realize high-system performance and reduce the chip area and the package pin numbers. Two LSI chips for the system, a single-chip processor, and a bit-sliced bus controller, are fabricated by a new n-channel MOS technology named the gate oxidation method (GOM) which provides a high-packing density, high speed, and a simplified process.     

Optimum design of 2-DOF parallel manipulators with actuation redundancy

The optimum design of 2-DOF redundant parallel manipulators is investigated in this paper. The planar 2-DOF parallel manipulator with actuation redundancy is treated as non-dimensional structure. The physical model of the solution space is studied. Based on the kinematic model and Jacobian matrix, the global conditioning index, global velocity index and global stiffness index of the 2-DOF parallel manipulators are investigated, and the geometrical parameters without dimension are determined. Based on the optimum non-dimensional result, the optimum dimensional parameters are achieved. The result of this paper is useful for the development of 2-DOF 3-RRR redundant parallel manipulators.     

Tight bounds on the redundancy of Huffman codes

A method for deriving optimal upper bounds on the redundancy of binary Huffman codes in terms of the probability p₁ of the most likely source letter is presented. This method will be used to compute bounds for all p₁⩾1/127, which were previously known only for a few special cases. Furthermore, the known optimal lower bound for binary Huffman codes is generalized to arbitrary code alphabets and some upper bounds for D-ary Huffman codes, 2⩽D<∞, are given, which are the tightest possible for all p₁⩾1/2     

On the implementation of minimum redundancy prefix codes

Minimum redundancy coding (also known as Huffman coding) is one of the enduring techniques of data compression. Many efforts have been made to improve the efficiency of minimum redundancy coding, the majority based on the use of improved representations for explicit Huffman trees. In this paper, we examine how minimum redundancy coding can be implemented efficiently by divorcing coding from a code tree, with emphasis on the situation when n is large, perhaps on the order of 10 ⁶. We review techniques for devising minimum redundancy codes, and consider in detail how encoding and decoding should be accomplished. In particular, we describe a modified decoding method that allows improved decoding speed, requiring just a few machine operations per output symbol (rather than for each decoded bit), and uses just a few hundred bytes of memory above and beyond the space required to store an enumeration of the source alphabet     

Bounds on the redundancy of binary alphabetical codes

An alphabetical code is a code in which the numerical binary order of the codewords corresponds to the alphabetical order of the encoded symbols. A necessary and sufficient condition for the existence of a binary alphabetical code is presented. The redundancy of the optimum binary alphabetical code is given in comparison with the Huffman code and its upper bound, which is tighter than bounds previously reported, is presented. The redundancy of the optimal alphabetical code is about 5% in comparison with the Huffman coding, which shows the usefulness of the alphabetical code     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

Optimum quantizers and permutation codes

Amplitude quantization and permutation encoding are two of the many approaches to efficient digitization of analog data. It is shown in this paper that these seemingly different approaches actually are equivalent in the sense that their optimum rate versus distortion performances are identical. Although this equivalence becomes exact only when the quantizer output is perfectly entropy coded and the permutation code block length is infinite, it nonetheless has practical consequences both for quantization and for permutation encoding. In particular, this equivalence permits us to deduce that permutation codes provide a readily implementable block-coding alternative to buffer-instrumented variable-length codes. Moreover, the abundance of methods in the literature for optimizing quantizers with respect to various criteria can be translated directly into algorithms for generating source permutation codes that are optimum for the same purposes. The optimum performance attainable with quantizers (hence, permutation codes) of a fixed entropy rate is explored too. The investigation reveals that quantizers with uniformly spaced thresholds are quasi-optimum with considerable generality, and are truly optimum in the mean-squared sense for data having either an exponential or a Laplacian distribution. An attempt is made to provide some analytical insight into why simple uniform quantization is so good so generally.     

16位MCU的市场机会

Microcontroller（微控制器）又称MCU或μC,是现代电子设备中不可或缺的核心器件之一,担负着控制、运算、信号转换及处理、通信等多项工作,人们日常生活中的大部分电器都或多或少地采用了不同架构、不同性能的MCU。     

集成有USB的增强型Wi-Fi芯片适宜新的应用

内建模拟数字转换器(ADC)的微控制器(MCU)已经在影像系统、工业控制、医疗仪器、科学仪表、无线基站和自动测试设备等领域被广泛应用.这种器件的技术升级路线无外乎沿着两个方向:一是选择功能更强大的微处理器芯核,如ARM等32位微处理器架构;另一个方向就是提升内部ADC的性能--在这个方面,Silicon Laboratories公司最近宣称在技术上有所突破,他们推出的C8051F064系列器件据称是业内首款内建16位ADC的MCU.     

A 16-bit specialized processor design

In this paper the ciruit and the design of an experimental 16 bits processor are described. The circuit is used in controller applications between mass storage devices and CPU of mainframes. The chip is fabricated in 2.5μ NMOS technology. This component (45 000 transistors, 35 mm², 40 pins) handles data generated by a CAD tool for real-time control system (PIASTRE).     

A 16 kbit smart 5 V-only EEPROM with redundancy

This paper describes several circuit techniques used in the design of a 5-V-only 16 Kbit EEPROM. The EEPROM uses a two transistor cell based on Fowler-Nordheim tunneling to a floating polysilicon gate. The EEPROM features 5-V-only operation, a self-timed program cycle with automatic erase before write, address and data latches, and a `ready' line output. These features make the program cycle timing compatible with static RAMs and simplifies the microprocessor interface. A new redundancy technique using EE cells as the programming element is also described.     

A 16 384-bit dynamic RAM

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.