The ultimate limits of CCD performance imposed by hot electron effects

It is shown that the ultimate speed of charge transfer in silicon charge coupled devices is limited by impact ionization in the silicon and the saturation of the drift velocity. The charge transfer speed of buried channel devices (BCCDs) decreases linearly with the separation, L, between centers of neighboring gates for L ≤ 10 μM. The decrease of the transfer speed of surface channel devices (SCCDs) is linear only for L ≤ 2 μm but is much faster for L > 2 μm. For L ≤ 2 μm, the ultimate charge transfer times of both SCCDs and BCCDs are about the same, corresponding to clock frequencies in the GHz range. Charge coupled devices made in small-energy gap compound semiconductors are also discussed. In spite of the higher carrier mobility, devices in these materials can not be operated at clock frequency above the KHz-MHz range due to interband impact generation of electron-hole pairs in the high electric field.     

A new short channel MOSFET structure (UMOST)

A new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described. The structure results in very short channel devices almost free of short channel effects and achieves higher speed without the use of submicron photolithography. A simplified theory for the structure is presented and compared with experimental results obtained on 1–10 μm channel length devices. This structure may prove useful in the study of conduction in short channel MOSFETs without introducing the complicating two dimensional short channel effects.     

Improved UHF power transistors in MOSFET IC-technology for portable radio applications

A power device for ultra high frequency use has been designed and fabricated in a standard 1.3 μm CMOS technology. A cell-based design is described for a compact and efficient power transistor layout. Devices with three different channel lengths (L = 1.1, 1.5 and 1.9 μm) were compared in the study. Breakdown voltage of > 18 V was achieved by adjusting the channel doping profile. On-resistance measures indicated R_ON 1–2 Ω for a 1 W estimated power output device. ƒ_T of up to 3.6 GHz and ƒ_max up to 10.5 GHz were extracted from small-signal s-parameter measurements. During class A measurements at 900 MHz, power gain of 7.8 dB for L = 1.5 μm devices and 9.5 dB power gain for L = 1.1 μm devices at V_d = 6 V were measured. Some devices were even able to deliver 11 dB power gain at moderate power levels (20 dBm). Maximum efficiency was around 40% and saturated output power was estimated to 24–25 dBm (250–300 mW) for the largest studied device (W/L = 2800/1.1).     

Low-frequency noise analysis of Si/SiGe channel pMOSFETs

Low-frequency noise characteristics of 0.1 μm Si_1−xGe_x channel pMOSFETs were studied by numerical simulations in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. Simulation results predict that Si_1−xGe_x channel pMOSFETs could offer improved low-frequency noise performance as compared to the conventional bulk Si devices. This improvement in Si_1−xGe_x channel pMOSFETs could be attributed to less effective oxide trap density for noise generation due to the increasing separation of quasi-Fermi level and valence band edge at Si–SiO₂ interface by Ge-induced band offset.     

Hole mobility enhancement and Si cap optimization in nanoscale strained Si1−xGex PMOSFETs

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si_1−xGe_x/Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si_1−xGe_x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length (L_G) Si_0.9Ge_0.1 PMOSFETs with SiO₂ gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si_1−xGe_x devices with L_G=70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.     

Ultra-small punchthrough MOSFET

A design for an ultra-small MOSFET is presented. MOSFETs with submicron channel lengths (L 0.25 μm) that operate with controlled punchthrough current are analyzed by two-dimensional numerical modeling. Current-voltage characteristics for subthreshold, nonsaturated and saturated regions of operation were obtained at various temperatures for devices of different channel length. The results indicate that device current is due to barrier-limited, space-charge-limited and surface-inversion conduction processes.     

Optimization of sub-0.1-μm offset Γ-shaped gate MHEMTs for millimeter-wave applications

We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors (MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated hydrodynamic simulation for the sub-0.1-μm offset Γ-gate In_0.53Ga_0.47As/In_0.52Al_0.48As MHEMTs shows a reasonable agreement with the electrical characteristics measured from the fabricated 0.1 μm devices. We have calibrated all the parameters using the measurement data with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-μm devices. Being simulated with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 μm, a gate length of 0.05 μm, a barrier thickness of 10 nm and a channel thickness of 12 nm.     

A practical device scheme for designing the dopant profile of source/drain extension region in sub-quarter-micron p-MOSFET's

A practical device scheme for designing sub-0.25 μm p-MOSFET's has been examined with respect to the dopant profile of source/drain (S/D) extension. Though shallow junction was reported to be helpless to reduce short channel effect for devices with the same effective gate length (L_eff), shallow-junction techniques are critically important to the practical device/process design for controlling the overlap of S/D extension with the gate. Adjusting the lateral dopant diffusion of S/D extension by other processes except shallow junction techniques may degrade the process control and the resultant performance for devices of the target gate length. In terms of a practical IC technology for sub-0.25 μm p-MOSFET's, an L_eff value properly smaller than the target gate length should be employed to well control the short channel effect and achieve the driving capability as large as possible. Hence, a scheme that properly adjusts the doping concentration for p-S/D extension formed by a given shallow-junction technique is significantly practical for designing the sub-0.25 μm p-MOSFET's with trade-off between driving capability and short channel effect.     

New evidence for velocity overshoot in a 200 nm pseudomorphic HEMT

It is believed that significant velocity overshoot effects are responsible for the high performance of pseudomorphic HEMTs (PsHEMTs). The overshoot is associated with the low effective mass in the InGaAs channel and the large Γ-L separation. Average channel electron velocities well in excess of 3.0 × 10⁷ cm/s have been predicted in Monte-Carlo PsHEMT simulations. However, average electron velocities extracted from transconductance measurements of such devices are much lower, typically in the range 1.5–2.0 × 10⁷ cm/s. In this paper we analyse real device measurements by using Monte-Carlo and drift diffusion simulations. We show clear evidence that the average velocity in the channel of a 200 nm PsHEMT fabricated in the Nano-electronics Research Centre of Glasgow University exceeds 3.0 × 10⁷ cm/s.     

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.     

Experimental characterization of most''s scaled down to the 1 μm level

Fundamental MOS device performances are experimentally analyzed for the projected three levels of scaled-down, silicon-gate devices envisioned in the next decade. The final third-level device having 20 nm thick gate oxide and 0.7 μm effective channel length will have vertical dimension only 0.35 times that of the present 3 μm lithography level. Principal device characteristics discussed are threshold voltage, source to drain breakdown voltage, and effective carrier mobility under practical applied voltage conditions, mainly for dynamic MOS memory operation.

It is found that breakdown voltage reduction is the main obstacle hindering down-scaling, and also that the mobility lowering in the shorter channel length region reduces the merits of down-scaling. MOS device performances for the coming 1 μm geometry level LSI's under practical operation conditions are discussed on the basis of the experimental results obtained.     

Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance

The electron mobility behaviour in submicron MOSFETs is studied in the temperature range of 77–300 K. As the effective channel length is reduced, the effective mobility as well as the field-effect mobility are found to decrease and to become less temperature dependent. These experimental results are explained by the influence of series resistance and effective channel length, which are both temperature dependent. The possibility of accurate determination of series resistance and “pure” mobility is demonstrated. A new method is proposed to determine submicron MOSFET channel length at low temperatures.     

Effect of the Ge-molefraction on the subthreshold slope and leakage current of vertical Si/Si1−xGex MOSFETs

The effect of the Ge-concentration on the subthreshold behaviour of vertical Si/Si_1−xGe_x pMOSFETs and of complementary Si_1−xGe_x/Si nMOSFETs is investigated by using an analytical model, which includes thermionic emission across the hetero-barrier. It is shown that inclusion of Si_1−xGe_x and strained Si in the source region of the pMOSFET and nMOSFET respectively, suppresses the subthreshold slope roll-up substantially and lowers the leakage current of even the smallest devices with channel lengths down to 50 nm.     

Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High-$kappa$ Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

In this letter, we report on measurements of carbon nanotube (CNT) field-effect transistors with high on/off ratio to be used as nonvolatile memory cells operating at room temperature. Thousands of memory devices have been realized using a complete in situ fabrication method. The self-aligned fabrication process allows large-scale production of CNT memory devices with high yield. The memory function is obtained by the threshold voltage shift due to the highly reproducible hysteresis in the transfer characteristics. The ratio of the current levels between a logical “1” and a “0” is about $hbox{10}^{6}$.      

Threshold shift calculations for ion implanted MOS devices

The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO₂ interface. These shallow implants (< 0.1 μm) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO₂ is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.     

Fabrication of vertical channel top contact organic thin film transistors

Vertical channel top contact (TC) organic thin film transistors (OTFTs) have been successfully realized on Si substrates with SiO₂ as gate insulators and P3HT(poly ∼3-hexylthiophene) as organic semiconductors. The active channel region was defined by a steep step through a Si etching method. Source and drain metal contacts were deposited by vacuum evaporation through a shadow mask at a high tilting angle. Top contact transistors with channel lengths 5 μm can be fabricated with a relatively simple and efficient (yield >85%) fabrication process with only two photolithography steps (two photo masks) while no need for high-resolution and precision alignment for channel definition. Measurement results showed that the vertical channel BC (bottom contact) devices have compatible performance with planar BC devices. However, vertical channel TC transistors showed improved performance with double field effect mobilities and three times larger current ON/OFF ratios than vertical channel BC devices.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

A voltage-dependent channel length extraction method for MOSFET’s

In this paper a new method for extraction of the channel length and channel resistance as a function of gate-voltage in MOSFET’s is introduced. The method is accurate and calculates the threshold voltages of all devices with different gate-lengths. The channel resistance is divided in two parts; the first part is a function of gate-voltage and threshold voltage difference (V_g − V_t) and the second part is only a function of gate-voltage. Further, the model determines the threshold voltage of short-channel devices independent of their parasitic resistances and implements the channel mobility as an arbitrary function of gate-voltage while the gate-voltage-dependent part of the resistance is uniquely separated from the first part of channel resistance for all devices.     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

A total resistance slope-based effective channel mobilityextraction method for deep submicrometer CMOS technology

A simple yet effective total resistance slope-based method for extracting the effective channel mobility in deep submicrometer CMOS technology is developed. Using the slope of the measured total resistance versus mask length, the series resistance is removed from the measured total resistance, and mobility is extracted without involving the effective channel length. The new method facilitates mobility extraction in situations where the effective channel length is difficult to extract, such as in lightly-doped-drain (LDD) devices or at low temperatures. The new method also allows the series resistance to be any function of the gate bias, making the mobility extraction in LDD devices easier and more accurate