Digitally assisted neural recording and spike detection multichannel integrated circuit designed in 180 nm CMOS technology

This paper presents design and measurement results of an integrated circuit dedicated to recording and detecting a wide range of biomedical signals. The chip is designed in 180 nm CMOS technology and occupies 1.5×1.5 mm². It consists of 8 channels responsible for amplification, filtration and detection of biomedical signals. In order to satisfy the requirements of a wide range of neurobiological experiments, the main parameters of a single recording channel, such as voltage gain, frequency band, voltage offset and threshold detection, are controlled independently by on-chip digital registers. The recording part is divided into two separate channels, i.e. an Action Potential (AP) stage and a Local Field Potential (LFP) stage. The voltage gain of the AP and LFP stages can be switched between 55.7/50.3 dB and 50.3/45.1 dB respectively. Corner frequencies of a particular stage can be digitally controlled in a wide range, i.e. the upper cut-off frequency can be changed in the 20 Hz–2 kHz (LFP stage) while the lower cut-off frequency can be tuned at the 120 mHz–3 kHz (LFP and AP stage). The upper cut-off frequency of the AP stage is equal to 6.9 kHz. In addition, the area of the analog part of the recording channel is 0.04 mm². A single recording channel is supplied from ±0.9 V and consumes about 4.8 µW of power while the Input Referred Noise is equal to 6.2 µV resulting in 4.92 of Noise Efficiency Factor (NEF).     

基于FPGA的实时基音周期估计系统

提出一种基于现场可编程门阵列FPGA的实时基音周期估计系统。语音信号先通过模数转换器转换成无符号位的8-bit的语音数字信号,然后,对每一帧语音信号进行电平削波,并将削波后的语音信号转换为带符号位的2-bit的数字信号,再采用自相关函数方法估计语音信号的基音周期,对一帧带符号位的2-bit的数字信号做自相关运算能够转换为简单的加法运算,只要用简单的组合逻辑电路和计数器就能够实现。使用SpartanIIXC2S30芯片将实时的基音周期估计算法用芯片内的存储器、门电路和时序电路实现,达到实时基音周期估计的目的。     

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.     

GaAs low-power integrated circuits for a high-speed digital signalprocessor

A high-speed 4-bit ALU, 4×4-bit multiplier, and 8×8-bit multiplier/accumulator have been implemented in low-power GaAs enhanced/depletion E/D direct-coupled FET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate MESFET process. The 4-bit ALU performs at up to 1.2 GHz with only 131-mW power dissipation. The multiplication time for the 4×4-bit array multiplier is 940 ps, which is the fastest multiplication time reported for any semiconductor technology. The 8×8-bit two's complement multiplier/accumulator uses 4278 FETs (1317 logic gates) and exhibits a multiplication time of 3.17 ns. the fastest yet reported for a multiplier of this type. Yield on the best wafer for the 4×4-bit and 8×8-bit circuits is 94 and 43%, respectively. A digital arithmetic subsystem has been demonstrated, consisting of the 8×8-bit multiplier/accumulator, two of the 4-bit ALUs, three logical multiplexers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 MHz     

新型多路数控增益放大器

介绍了一种新型多路数控增益放大器。该放大器具有8路模拟信号输入通道,采用3位数字信号控制通道位;每个通道均具有256级增益控制,采用8位数字信号控制放大倍数;输入信号采用绝对值处理电路,具备极性判别信号输出。采用多芯片微组装技术实现,体积小、重量轻,可用做小型微机处理电路的模拟接口芯片。简要介绍了基于该放大器的某设备控制与保护系统的应用示例。     

Bi-Fi: an embedded sensor/system architecture for REMOTE biological monitoring.

Wireless-enabled processor modules intended for communicating low-frequency phenomena (i.e., temperature, humidity, and ambient light) have been enabled to acquire and transmit multiple biological signals in real time, which has been achieved by using computationally efficient data acquisition, filtering, and compression algorithms, and interfacing the modules with biological interface hardware. The sensor modules can acquire and transmit raw biological signals at a rate of 32 kb/s, which is near the hardware limit of the modules. Furthermore, onboard signal processing enables one channel, sampled at a rate of 4000 samples/s at 12-bit resolution, to be compressed via adaptive differential-pulse-code modulation (ADPCM) and transmitted in real time. In addition, the sensors can be configured to filter and transmit individual time-referenced "spike" waveforms, or to transmit the spike height and width for alleviating network traffic and increasing battery life. The system is capable of acquiring eight channels of analog signals as well as data via an asynchronous serial connection. A back-end server archives the biological data received via networked gateway sensors, and hosts them to a client application that enables users to browse recorded data. The system also acquires, filters, and transmits oxygen saturation and pulse rate via a commercial-off-the-shelf interface board. The system architecture can be configured for performing real-time nonobtrusive biological monitoring of humans or rodents. This paper demonstrates that low-power, computational, and bandwidth-constrained wireless-enabled platforms can indeed be leveraged for wireless biosignal monitoring.     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

面向音频应用的可配置片上系统的设计与实现

基于一款通用的16位定点数字信号处理器,结合D/A转换器、A/D转换器和放大器等模拟电路模块,设计并实现了一种面向音频应用的可配置片上系统.该系统支持立体声输入输出,具有8～48 kHz之间可编程的采样频率,以及可编程的输入输出放大器增益.同时,设计使用了24位高精度Σ-Δ A/D转换器,并配有可供选择的数字滤波器.为支持不同应用,系统提供24位或16位的可编程字长调节.系统芯片工作在1.8 V电压下,芯片内各部分支持挂起或睡眠状态,有利于低功耗的便携式应用开发.介绍了部分关键功能模块的仿真、验证和测试,以及整个系统仿真模型的建立.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

An Ultra-Low Noise Microwave Synthesizer

A silicon bipolar transistor together with a barium titanate dielectric resonator were used to design a low noise microwave synthesizer. The oscillator was phase locked to a low-frequency (LF) reference with microwave frequency selection provided by a high-speed digital programmable divider within the phase-locked loop. The resulting FM noise Delta f/sub rms/ was 0.0003 Hz in a 1-Hz band greater than 1000 Hz from the 1-GHz carrier.     

A Digital Telephone with Extensions

A digital telephone concept is described where each subscriber set sends and receives digital signals (8-bit PCM). Duplex, simultaneous operation of extensions on a single pair of wires is made possible by time division multiplex (TDM) techniques. A successful feasibility demonstrator of the concept that operates at 512 kbits/s is also described. It has a digital switch at one end and digital telephones at the other, with up to three extensions talking at one time. The telephones feature a separate digital signaling channel, automatic loop-back testing, and low-power transducers.     

Voice low tone to high tone ratio: a potential quantitative index for vowel [a:] and its nasalization

Hypernasality is associated with various diseases and interferes with speech intelligibility. A recently developed quantitative index called voice low tone to high tone ratio (VLHR) was used to estimate nasalization. The voice spectrum is divided into low-frequency power (LFP) and high-frequency power (HFP) by a specific cutoff frequency (600 Hz). VLHR is defined as the division of LFP into HFP and is expressed in decibels. Voice signals of the sustained vowel [a :] and its nasalization in eight subjects with hypernasality were collected for analysis of nasalance and VLHR. The correlation of VLHR with nasalance scores was significant (r = 0.76, p < 0.01), and so was the correlation between VLHR and perceptual hypernasality scores (r = 0.80, p < 0.01). Simultaneous recordings of nasal airflow temperature with a thermistor and voice signals in another 8 healthy subjects showed a significant correlation between temperature rate of nasal airflow and VLHR (r = 0.76, p < 0.01), as well. We conclude that VLHR may become a potential quantitative index of hypernasal speech and can be applied in either basic or clinical studies.     

A digital pixel image sensor for real-time readout

An experimental digital image sensor that converts analog video signals into 8-bit digital signals for each unit pixel, and reads out the signals at an operating clock of standard TV has been developed. Each pixel is equipped with a photodiode, a 1-bit analog-to-digital converter (1-bit ADC), an 8-bit pulse counter, and a signal processing circuit. The sensor system displays a two-dimensional (2-D) image in real time. The 1-bit ADC has a dynamic range of 110 dB at an operating voltage of 1.3 V. “Knee” characteristics and the results of an investigation into random noise sources in the circuit are also described     

A Per-Channel A/D Converter Having 15-Segment µ-255 Companding

This paper describes a companded analog-to-digital (A/D) converter for voiceband signals that is simple and potentially inexpensive. The converter uses only 18 coarsely spaced analog levels. Fine resolution is obtained by oscillating between these levels at an increased speed and averaging the result over a Nyquist interval. The companding used in the converter is effectively the same as that of μ-255 pulse-code modulation (PCM). In the encoding process a one-bit code is generated at 256 000 samples/s. This 1-bit per sample signal can be transmitted and decoded directly, or a simple digital circuit will produce a 13-bit, 8-kHz linear PCM signal that can be compressed to 8-bit companded PCM format. In this paper the basic operation of the 1-bit coder is described and its performance when connected to a 1-bit decoder is illustrated. Methods for obtaining both linear and compressed PCM are then presented, and the properties of these PCM signals with respect to noise, gain tracking, and harmonic content are described. Relative insensitivity to circuit component variations, absence of analog gates, along with the need to generate only a few analog levels, make the coder especially well suited to integrated circuit realization.     

On the design of highly linear CMOS digitally programmable operational transconductance amplifiers for low and high-frequency applications

This paper proposes a novel highly linear digitally programmable fully differential operational transconductance amplifier (DPOTA) circuit. Two versions of the proposed DPOTA structure are designed. The first version is optimized for high-frequency operation with current division networks designated to 3-bit control code words. On the other hand, the second version is optimized for low-frequency operation with 4-bit control code words. The third-order harmonic distortion (HD3) of the first DPOTA version remains below ? 66 dB up to 0.4 V differential input voltage at 10 MHz frequency. The second DPOTA version achieved HD3 of ? 70 dB with an amplitude of 20 mV_p–p and at 100 Hz frequency. The proposed circuits are designed and simulated in 90 nm CMOS model, BSIM4 (level 54) under a balanced 1.2 V supply voltage.     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

A wireless microsystem with digital data compression for neural spike recording

The paper describes a multi-channel neural spike recording system sensing and processing the action potentials (APs) detected by an electrode array implanted in the cortex of freely-behaving small laboratory animals. The core of the system is a custom integrated circuit (IC), with low-noise analog front-end interfaced to a 16 electrode array followed by a single 8-bit SAR ADC, a digital signal compression and a 400-MHz wireless transmission units. Data compression is implemented by detecting action potentials and storing up to 20 points per each spike waveform. The choice greatly improves data quality and allows single spike identification. The transmitter delivers a 1.25-Mbit/s data rate coded with a Manchester-coded frequency shift keying (MC-FSK) within a 3-MHz bandwidth. An overall power consumption of 17.2 mW makes possible to reach a transmission range larger than 20-m. The IC is mounted on a small and light printed circuit board. Two AAA batteries, set in a pack positioned on the back of the animal, power the system that can work continuously for more than 100 h.     

Charge-coupled digital circuits

This paper describes the operation and the applications of charge- coupled shift registers for digital signals. Simple signal-regeneration stages for digital charge-coupled shift registers are analyzed and their operation is demonstrated by charge-coupled circuits made by a p-MOS process. A charge-transfer efficiency of about 99.6 percent per electrode at a clock frequency of 1 MHz was obtained in the operation of three-phase 8-bit shift registers made by the p-MOS process. Silicon-gate construction is proposed for achieving high- performance high-density structures and also two-phase charge-coupled devices.     

A high-speed digitally programmable CCD transversal filter

A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible.     

Focal-Plane Spatially Oversampling CMOS Image Compression Sensor

Image compression algorithms employ computationally expensive spatial convolutional transforms. The CMOS image sensor performs spatially compressing image quantization on the focal plane yielding digital output at a rate proportional to the mere information rate of the video. A bank of column-parallel first-order incremental DeltaSigma-modulated analog-to-digital converters (ADCs) performs column-wise distributed focal-plane oversampling of up to eight adjacent pixels and concurrent weighted average quantization. Number of samples per pixel and switched-capacitor sampling sequence order set the amplitude and sign of the pixel coefficient, respectively. A simple digital delay and adder loop performs spatial accumulation over up to eight adjacent ADC outputs during readout. This amounts to computing a two-dimensional block matrix transform with up to 8times8-pixel programmable kernel in parallel for all columns. Noise shaping reduces power dissipation below that of a conventional digital imager while the need for a peripheral DSP is eliminated. A 128times128 active pixel array integrated with a bank of 128 DeltaSigma-modulated ADCs was fabricated in a 0.35-mum CMOS technology. The 3.1 mm times 1.9-mm prototype captures 8-bit digital video at 30 frames/s and yields 4 GMACS projected computational throughput when scaled to HDTV 1080i resolution in discrete cosine transform (DCT) compression