Titanium silicide/silicon nonohmic contact resistance for NFET's,PFET's, diffused resistors, and NPN's in a BiCMOS technology

Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the body of diffused resistors, and into the active region of NPN's through the titanium silicide/silicon interface. This contact resistance can represent a significant fraction of the total device resistance for devices of small dimensions, and contributes to a loss in circuit performance. The impedance of this interface is a function of the doping level in the silicon immediately below the interface, and this doping level is a sensitive function of the heat applied to the structure after the formation of the silicide. The correspondence of FET series resistance, emitter resistance, the diffused resistor end effects and the non-ohmic nature of a contact after heat is applied is presented. Use of a rapid thermal anneal to obtain the requisite silicide characteristics while minimizing the impact on the contact resistance is demonstrated for a 0.8-μm BiCMOS technology     

Titanium silicide-silicon interface degradation during heat treatment

Thin titanium silicide films were grown on different silicon substrates by rapid thermal annealing in a nitrogen ambient. The silicide films were then annealed in a furnace at high temperature in a nitrogen ambient for various times. The effect of such heat treat-ment on the morphology of titanium silicide surface and the titanium silicide-silicon interface was studied. It is proposed that the morphological change is primarily due to the diffusion of silicon and/or dopant impurities via grain boundaries of the silicide. There is a strong correlation between the surface of the titanium silicide film and that of the titanium silicide-silicon interface.     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

Multiple-pulse laser thermal annealing for the formation of Co-silicided junction

Formation of Co-silicide contact layers on narrow silicon regions using multiple-pulse excimer laser annealing is demonstrated. Excellent performance of junction leakage behavior can be attained on narrow-width n/sup +//p and p/sup +//n junction as compared with standard rapid thermal annealed samples. Liquid-phase epitaxial Co-silicide regrowth has been found to occur and create a smooth and abrupt silicide/Si interface with high junction integrity using multiple-pulse laser annealing. Heat confinement created by the shallow trench isolation surrounding the narrow-width n/sup +//p and p/sup +//n junctions has minimized rapid quenching that might result in an amorphous structure. This has facilitated the crystallization of Co-silicide with multiple-pulse laser annealing.     

Anomalous scaling effect of tungsten/titanium nitride/titanium to silicon electrical contact resistance for subquarter micron microelectronic devices

This paper reports the anomalous scaling effect of tungsten/titanium nitride/titanium to (a) n+ and (b) p+ silicon electrical contact resistance in dynamic random access memory (DRAM) devices, upon post heat treatment following rapid thermal silicidation annealing. The electrical measurements on contacts of sizes ranging from 0.54 μm to 0.18 μm reveal that the increase in resistance becomes larger as the contact size decreases. Transmission electron microscopy (TEM) results show that the silicide film agglomeration proceeds more severely as the contact size decreases. To explain the size-dependent degradation of the contact resistance, numerical simulation of the shape evolution of the silicide film is performed. The results show that the poor film coverage, especially at the edge, accelerates the reduction rate in contact area.     

New salicidation technology with Ni(Pt) alloy for MOSFETs

A novel salicide technology to improve the thermal stability of the conventional Ni silicide has been developed by employing Ni(Pt) alloy salicidation. This technique provides an effective avenue to overcome the low thermal budget (<700°C) of the conventional Ni salicidation by forming Ni(Pt)Si. The addition of Pt has enhanced the thermal stability of NiSi. Improved sheet resistance of the salicided narrow poly-Si and active lines was achieved up to 750°C and 700°C for as-deposited Ni(Pt) thickness of 30 nm and 15 nm, respectively. This successfully extends the rapid thermal processing (RTP) window by delaying the nucleation of NiSi₂ and agglomeration. Implementation of Ni(Pt) alloyed silicidation was demonstrated on PMOSFETs with high drive current and low junction leakage     

Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

The effects of thermal nitridation conditions on the reliability of thin nitrided oxide films

MIS capacitors on n-type silicon substrate with thin oxide films thermally nitrided in NH3gas ambient at different temperatures and for different times have been fabricated. The effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress. It is found that the oxide films nitrided at 900°C exhibit much improved total charge to breakdown and interface trap generation if proper nitridation time is used. The superior characteristics of the fabricated nitrided oxide films using the proposed optimum conditions are suitable for existing CMOS/VLSI applications.     

Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

Rapid thermal nitridation of thin SiO2 films

An alternative to SiO₂ for gate dielectric applications in MIS devices is nitrided silicon dioxide. A study of this material is presented in this paper. Thin SiO₂ layers (10 nm minimum thickness) were grown on silicon substrates and subsequently nitrided in ammonia at 1 atm using a rapid thermal processing system. Nitridation times ranged from 3 sec to 60 sec at temperatures from 900 to 1200‡ C. The resulting films were then characterized using a variety of techniques including high resolution TEM, XPS, AES, SIMS, and electrical measurements (C-V). Higher temperatures and longer processing times resulted in the accumulation of nitrogen at the film surface and at the Si/SiO₂ interface. As expected, the electrical characteristics of the nitrided films were strongly influenced by the processing conditions. The morphology of the interface, as revealed by high-resolution TEM, was also altered by the nitridation process, especially for high processing temperatures (>1000° C).     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Formation of silicided,ultra-shallow junctions using low thermal budget processing

The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.     

Salicides: materials, scaling and manufacturability issues for future integrated circuits (invited)

In this paper we present an overview of the development of advanced salicide processes at Texas Instruments, addressing both Ti and Co salicides. Scaling issues, such as sheet resistance of deep sub-micron structures for Ti salicide and diode leakage on shallow junctions for Co salicide, are discussed, as well as processes developed to overcome these issues. The key material aspects controlling these variables are reviewed, such as Ti silicide phase formation and transformations and mechanisms of direct formation of C54 TiSi₂, which control sheet resistance, and silicide–silicon interface characteristics for Co salicide, impacting diode leakage. Implementation and manufacturability aspects are also discussed. We present advanced Ti and Co salicide processes with manufacturing and high yield capability demonstrated for sub-0.25 μm CMOS technologies. Process modifications that extend the applicability of these salicides to 0.1 μm CMOS are also presented.     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

Thermal Nitridation of Si and SiO/sub 2/ for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO/sub 2/. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO/sub 2/ in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized using I-V, C-V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, and C -V measurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-dowm VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO/sub 2/ and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO/sub 2/-Si interfaces.     

Characteristics of thermally nitrided silicon dioxide film and plasma enhancement

After reviewing characteristics of thermally nitrided silicon dioxide films, plasma enhanced nitridation is described. The plasma technique makes possible reduction of the nitridation temperature by activating reaction species. Silicon dioxide films of about 10 nm thickness were nitrided in ammonia gas plasma, for example, at 1000‡C and at a pressure of 40 Pa. From the results of the AES depth profiles and the N_ss distribution, good dielectric and interfacial properties have been obtained via plasma nitridation. The plasma nitroxide films are useful for gate insulators of small MOSFETs in future VLSI.     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

Novel submicrometer MOS devices by self-aligned nitridation of silicide

A new MOS technology is developed for submicrometer MOS devices. In this new technology, TiSi2is formed on the source and drain diffused layers by self-aligned silicidation to reduce the sheet resistance, and TiN is formed in the contact holes by self-aligned nitridation of TiSi2. This TiN can be used as an effective barrier metal between Al and Si. TiSi2is prepared by a two-step annealing method to prevent a reaction between Ti and the field oxide. PSG cap annealing after TiSi2formation provides excellent p-n junction characteristics and relatively low silicide sheet resistance of 4 ω/□ even after annealing at 950°C for 30 min. TiN is formed by direct thermal nitridation of TiSi2in N2ambient at a temperature higher than 900°C after contact hole formation. The formation of TiN is confirmed by AES, ESCA, and X-ray diffraction analysis. The TiN formed by direct thermal nitridation is found to prevent Al diffusion into the Si substrate even for post-metallization annealing at 500°C for 1 h. The characteristics of devices fabricated by this new technology also are determined.     

氮化SiO2中的电子陷阱和Fowler-Nordheim隧穿压力下陷阱中心的产生(英文)

Electron trapping and trap center generation within thermally nitrided oxides are investigated using Fowler-Nordheim constant current stress and avalanche electron injection methods. The results show that electron traps created in the films during the nitridation increase with the nitridation time. The positive charges build up near the interface accompanied with the generation of the new electron trap centers in the films under Fowler-Nordheim tunneling stress. The generation mechanisms are proposed in this paper.