基于FPGA的积分型数字锁相环的设计与实现

位同步时钟信号的提取是通信系统中的关键部分,应用数字锁相环可以准确地从输入码流中提取出位同步信号.本文简要介绍了数字锁相环的基本原理,在详细介绍了积分型超前—滞后数字锁相环的工作原理的基础上,利用VHDL语言对该系统进行了设计,给出了数字锁相环路主要模块的设计方法及仿真结果,得到了该系统的顶层电路,其中重点分析了积分型数字鉴相器的原理,给出了设计过程；并根据系统的参数进行了性能分析,最后给出了整个系统的功能仿真结果.具有一定的工程实用价值.     

基于FPGA的数字基带传输位同步恢复

提出了一种基于全数字锁相环提取数字基带传输位同步时钟的设计方案,该方案采用环路鉴相器产生误差信号控制本地位同步电路的添加/扣除门在时钟输出的脉冲序列中附加或扣除1个或几个脉冲实现同步。给出了该方案的整体电路,并经VHDL程序设计,在MaxplusⅡ环境下做了时序仿真,从仿真结果分析了设计方法可实现数字基带传输位同步时钟的提取。     

GPS/GLONASS同步的可编程逻辑实现

给出了一种用于第三代移动通信系统(3G)CDMA2000基站的时钟同步方案。由一个双星接收卡接收GPS/GLONASS标准秒信号作为整个时钟同步系统的参考,分两级锁相环实现:第一级锁相环采用软件锁相,输出10MHz信号作为第二级锁相环的参考源,第二级锁相环为2个模拟锁相环,分别输出16fc和48fc(fc=1.2288MHz)。2S信号由16fc分频得到。这种设计保证了输出时钟的长期稳定性和短期稳定性,满足协议所规定的同步精度。详细介绍了数字鉴相器、2S产生电路、相差检测及控制电路的电路设计和有关仿真结果。     

CDMA2000基站GPS/GLONASS同步的可编程逻辑实现

给出了一种用于第三代移动通信系统(3G)CDMA2000基站的时钟同步方案。由一个双星接收卡接收GPS/GLONASS标准秒信号作为整个时钟同步系统的参考,分两级锁相环实现。该设计保证了输出时钟的长期稳定性和短期稳定性,满足协议所规定的同步精度。详细介绍了数字鉴相器、2s产生电路、相差检测及控制电路的电路设计和有关仿真结果。     

实用快捕数字锁相环

锁相环(PLL)能从受噪声干扰的输入信号中提取相干信息,因此广泛应用于数字通信、雷达、遥测等领域中。近来,数字锁相环(DPLL)因便于采用数字集成电路,装配调试方便,而得到了迅速发展。本文介绍的是用于四相数字移相键控(QPSK)调制器中,作位定时提取用的数字锁相环。它能较好地解决锁相环设计中的一对基本矛盾:捕捉时间要短(即捕捉带宽大),抗噪声性能要好(即相位抖动小)。在介绍电路组成前,先回顾一下一般数字锁相环的组成和工作原理。数字锁相环框图如图1所示,输入信号经“过零检测”后形成一个窄脉冲序列 I′_n,它与本地产生的钟脉冲序列 Q_分在鉴相器中进行相位比较。如 Q_分超前 I′_n,     

时钟提取与抖动衰减数字锁相环设计研究

文章简要介绍了数字锁相环(DPLL)的工作原理,重点提出了用于V5接口芯片中的时钟提取锁相环和抖动衰减锁相环的设计,并对其进行了分析．     

GPS中频接收机同步的实现

介绍了一种GPS接收机的同步实现仿真过程,由于捕获部分采用FFT变换方法,大大缩短了捕获时间,码跟踪采用数字延迟锁相环（DPLL）,载波跟踪采用数字锁相环（DPLL）,位同步采用了一种计算所有可能比特跳变位能量的最大似然位同步算法,可以在极低的信号与噪声功率谱密度之比的条件下,检测到比特位边界。     

一种新型的单相数字锁相环

本文提出了一种新型的高精度数字锁相环（DPLL）技术,以一个改进的鉴相器（PD）环节代替常用的二阶通用积分器构成的PD环节,为了抑制该方法在同步信号频率上引入的二次谐波干扰,本文分析了引入谐波的原因,提出针对同步信号频率二次谐波的带阻滤波器,并研究了基于FPGA的数字锁相环实现方法。该方法锁相精度高,速度快,结构简单,计算量较小。仿真和实验结果表明该方法是有效可行的。     

视频处理器中电荷泵锁相环设计

为产生一个与视频信号中的行同步信号严格同步的时钟信号,设计了一种数模混合结构的电荷泵锁相环(PLL)电路。通过对锁相环电路中鉴频鉴相器、电荷泵电路、振荡器电路设计适当改进,实现了性能稳定的时钟信号。采用中芯国际公司的0.35μm 2P4M双层多晶硅四层金属3.3 V标准CMOS工艺,使用Simulink软件进行了系统级仿真、Spectre软件进行了电路级仿真、Hsim软件进行了混合仿真。结果表明,环路输出频率27 MHz时钟信号,占空比达到50.141%,输入最大2 Gbit/s像素信号条件下,时钟抖动小于350 ps,锁定时间小于30μs,芯片的工作达到设计要求。     

基于FPGA同步电路的实现

同步是通信系统中一个重要的问题.在数字通信中,除了要获取相千载波的载波同步外,位同步的提取是更为重要的一个环节.介绍了一种基于FPGA同步电路的实现而提出一种数字锁相环的位同步提取电路的方案,并已成功地用FPGA器件实现了此方案.此时钟提取电路可以快速、准确地对串行输入信码进行位同步时钟的提取,即使输入码流中有毛刺现象...     

基于FPGA的DDS＋DPLL跳频信号源设计

针对跳频通信系统有固有噪声的特点,结合DDS＋DPLL高分辨率、高频率捷变速度的优点,并采用Altera公司的Quartus-Ⅱ_10.1软件进行设计综合,提出了一种新型的跳频信号源。结果表明,该设计中DPLL时钟可达到120MHz,性能较高,而仅使用了30个LUT和18个触发器,占用资源很少。     

Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception

A fast clock synchroniser that quickly adjusts the initial phase of the DPLL output clock to the input signal (receiver detector output) at the beginning of acquisition is proposed for burst QDPSK signal reception. The synchroniser performance is given in terms of nondetection rate (NDR) of the unique word following the clock synchronisation preamble. Measured results clearly indicate that the proposed synchroniser achieves faster synchronisation than the conventional binary quantised DPLL clock synchroniser.<>     

Slot clock recovery in optical PPM communication systems withavalanche photodiode photodetectors

Slot timing recovery in a direct-detection optical PPM communication system can be achieved by processing the photodetector output waveform with a nonlinear device whose output forms the input to a phase-locked loop. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The RMS phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (λ=834 nm) and a silicon avalanche photodiode photodetector. The system used Q =4 PPM signaling and operated at a source data rate of 25 Mb/s. The mathematical model developed to compute the RMS phase error of the recovered clock is shown to be in good agreement with results of actual measurements of phase errors. The use of the recovered slot clock in the receiver resulted in no significant degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10^-6 at a received optical signal energy of 55 detected photons per information bit     

基于FPGA的光纤通信系统中帧同步头检测设计

为实现设备中存在的低速数据光纤通信的同步复接／分接,提出一种基于FPGA的帧同步头信号提取检测方案,其中帧头由7位巴克码1110010组成,在数据的接收端首先从复接数据中提取时钟信号,进而检测帧同步信号,为数字分接提供起始信号,以实现数据的同步分接。买验表明,此方案成功地在光纤通信系统的接收端检测到帧同步信号,从而实现了数据的正确分接。     

Evaluation of cellular mobile telephone data receivers

Some measurement techniques and results employed to evaluate advanced mobile phone system (AMPS) data receivers being driven by a Rayleigh fading channel are described. These performance measurements were used as a mechanism for comparing the design effectiveness of various bit clock recovery systems. Of five data receiver types evaluated, two models employed a full-wave rectifier in the bit clock recovery system. In this system nominal diode unbalance may cause the derived bit clock to lock 180° from the phase required to properly decode the incoming bit stream. This condition may even occur at high carrier-to-noise ratios when message structures containing long strings of ones or zeros are received. The other data receiver types employed digital signal processing for clock recovery to circumvent this phase ambiguity problem. The performance data of five data receivers are compared to noncoherent frequency-shift keying (FSK) as a model. In most cases, the test results are in good agreement with this model. The performance measurements presented include derived clock jitter and single and average bit error rates as a function of average carrier-to-noise ratios. The implementation of test instrumentation and the interpretation of test results are discussed. The objective is to stress the capability of simulation measurements to evaluate mobile receiver designs in a laboratory environment.     

Word timing recovery in direct detection optical PPM communicationsystems with avalanche photodiodes using a phase lock loop

A technique for word timing recovery in a direct detection optical pulse position modulation (PPM) communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an AlGaAs laser diode transmitter (λ=833 nm) and a silicon avalanche photodiode photodetector, and its used Q=4 PPM signaling at a source data rate of 25 Mb/s. The mathematical model developed to characterize system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock, along with a slot clock recovery system described previously, caused no measurable penalty in receiver sensitivity when compared to a receiver which used common transmitter/receiver clocks. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10^-6 at less than 60 average detected photons per information bit     

Supervisory signal transmission by modulating the mB1C codecomplementary bit

A supervisory signal transmission method for digital optical communication systems is proposed. It minimizes circuit scale, clock frequency increase, and interference between traffic and supervisory information, and does not require customization. The supervisory signal is carried by the amplitude-modulated complementary bit in the mB1C coded sequence. The code adds a single bit after every m bit block as a complement to the last bit of the block. Clock frequency increase is kept at a level of (m+1)/m. This additional bit is called the C bit. If the C bit's amplitude is modulated according to the supervisory (SV) signal and the main data block is not modulated, traffic and supervisory information can be isolated in time over the same fiber transmission     

Efficient time gating in ultrafast optical TDM networks

Ultrafast optical communication is the backbone of high-speed global networking infrastructure. Optical time division multiplexing (OTDM) is a popular technique for embedding data from many simultaneous users on a single optical channel. This paper studies the optimal clock signal used in optical time gating to extract the data of the desired user in an OTDM network. We show that the pulse width of the clock signal can be optimized to achieve a minimum bit error rate (BER) in these networks. In this paper, we assume that the optical clock signal used for time gating has jitter, and there is therefore a delay variation between the clock and data signals. We model this delay as a zero mean Gaussian random variable. Using this model, an analytical BER expression is derived for systems with Gaussian pulses. In the numerical results, we find the optimal values of the clock pulse width by evaluating the BER versus the pulse width for different variances of the delay. Simulation results are also presented to evaluate the accuracy of the analytical expression.     

数字锁相环在位同步提取中的应用

在数字通信中,为保证信息传输和交换的正确,各种数字模块的时钟应该具有相同的频率,否则在数据传输中会产生滑动、误码,直至通信中断。本文详细论述了基于FPGA技术实现数据码流位同步时钟信号的提取,以及电路模块的工作原理、关键技术和实现途径,并通过了软件仿真。