A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

适于视频应用的高数据传输率集成CMOS收发机

这篇文章给出了一个5GHz CMOS射频收发机的设计方案。此设计采用0.18微米射频CMOS加工工艺,集合了最新IEEE802.11n的特性例如多输入多输出技术的专利协议以及其他无线技术,可提供应用在家庭环境中的实时高清电视数据的无线高速传输。设计频率涵盖了从4.9GHz到5.9GHz的ISM频带,每个射频信道的频宽为20MHz。收发机采用了直接上变频发射器和低中频接收器的结构。在没有片上校准的情况下,设计采用双正交直接上变频混频器,得到了超过35dB的镜像抑制。测试结果得到6dB接收机噪声系数以及在-3dBm输出功率时得到发射机EVM结果优于33dB。     

Fully integrated blue/UV SOI CMOS photosensor for biomedical and environmental applications

In this paper, we present a microsystem for measuring optical power in blue/UV wavelengths (from λ = 200 nm to λ = 450 nm) which includes a photodiode and the analog processing circuit of the photodiode signal, fully integrated in 2 μm SOI CMOS technology. The photodiode has a maximum responsivity for λ = 400 nm. Th photosensor functions as a current to frequency converter. Measurements of the microsystem illuminated by blue and UV LEDs demonstrate the good linear behavior, sensitivity and efficiency of the system.     

Fully integrated dual-band VCOs with power controlled by body voltage in 130 nm CMOS/SOI for multi-standard applications

In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were −89 and −93 dBc/Hz at 5.2 and 3.6 GHz respectively.     

一种SOI CMOS/LDMOS单片智能功率集成电路

介绍了一种单片智能功率硅集成电路的设计和制造工艺，该电路包括工作于9V低压的常规CMOS管和两个最高耐压为80V、电流通过能力大于3A的LDMOS管。电路采用SOI介质隔离CMOS／LDMOS工艺，芯片面积约50mm^2。基于一种简单的二维模型，认为，在功率集成中，纵向导电的VDMOS管由于其导通电阻有一个自限制特点，因此并不特别适合智能功率集成。     

13.56 MHz CMOS transceiver for RFID applications

An Amplitude Shift Keying (ASK) transceiver for RFID applications is presented in this paper. The proposed transceiver is suitable for communications with electronic devices that are powered through an inductive link. The circuit has been designed to be compatible with the communication standards ISO 14443. It operates at 13.56 MHz with a communication speed from 200 kHz up to 847 kHz. In modulation mode of operation, a solution based on programmable CMOS inverters is proposed to control the modulation depth in the range [0–100%]. The demodulator has been designed using versatile current rectifier and a simple operational transconductance amplifier stage. The proposed transceiver was implemented in a standard 0.5 μm CMOS process. The circuit covers an area of 2 mm² and the total DC power consumption is lower than 5.3 mW under 4V DC supply voltage. Stéphane Meillére has received the Engineer degree in Microelectronics from the ISEN-Toulon, Institut Supérieur d’Electronique et du Numérique, School at Toulon in 2000 and the M.Sc. and Ph.D. degrees from the University of Provence Aix-Marseille I, France, in 2000 and 2004, respectively, all in Microelectonics. From 2003 to 2005, he worked as a Research Engineer at the ISEN-Toulon. Since 2005 he joined the University of Provence as an Assistant Professor. His research interests are mainly in the design of full custom ASICs. He integrated in the same time the Integrated Circuits Design Team at the L2MP laboratory. He worked on different research project with industry. Hervé Barthélemy has received the MSc degree in Electrical Engineering in 1992 and the PhD degree in Electronics from the University of Paris XI Orsay, France in 1996. In 2002 he received the HDR degree from the University of Provence, Aix-Marseille I, France. From 1996 to 2000 he was an Assistant Professor at the Institut Supérieur d’Electronique de la Méditerranée (ISEN) in Toulon, France. Since 2000 he joined the University of Provence where is has been a full Professor in 2005. Since 2005 he has headed the Integrated Circuits Design Team at the L2MP laboratory. The team counts 12 Researchers and 20 PhD students and is involved in several research projects with industry. His research interests are mainly in the design of radiofrequency analog integrated circuits. He authored and co-authored multiple publications in international journals and conference proceeding. Michel Martin received an engineering degree in applied physics, option Micro-electronics from Ecole Nationale Supérieure de Physics in Marseille in 1991. He worked previously in ST Microelectronics, and he was involved in the design of the Smart Card Group’s product. He joined Gemplus in ’91 where he designed chips for secured smart cards memories. In 1995, he was the Co-founder of INSIDE Contactless. He was involved in the analog and EEPROM memories designs for contact and contactless chips. Michel was promoted I.C. Design Director with a team of 15 people divided on 2 Design Centers. He still maintains an active part in the chip Design. He is also the responsible for technical interface with the foundries to develop EEPROM memory bit cell, and improve the new processes dedicated the smart cards application.     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

The circuit and functional blocks for radiation-hard transceiver LSICs in SOI CMOS

The results of designing a set of basic circuit and functional blocks (amplifying, oscillating, mixing, etc.) to construct the radiation-hard transceiver CMOS Silicon-on-Insulator (SOI) large-scale integration circuits (LSICs) are presented. It was established experimentally that the test chips of the circuit and functional blocks (CFBs) produced by domestic CMOS SOI technologies at a feature size of 0.35 µm are functionally operable in the frequency range of 1 MHz to 1.8 GHz, and the values of the main parameters are close to the calculated ones. The results of the experimental research on the hardness of the developed CFBs to pulse and dose impact of ionizing radiation are presented and the hardness levels were evaluated.     

LDMOS in SOI technology with very-thin silicon film

In this paper, we extensively investigate, by two-dimensional simulations, the output characteristics accuracy and breakdown voltage performance for very-thin film (80 nm) SOI lateral double-diffused MOS (LDMOS) transistor as a function of the drift doping, drift length and field plate length. Trade-offs are discussed to optimize the off-state breakdown voltage versus the occurrence of kink effect and quasi-saturation in on-state. The conclusions are supported by experimental results.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

An auto-I/Q calibrated CMOS transceiver for 802.11g

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1/spl deg/ and gain mismatch to 0.1dB. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point.     

Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.     

Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz

In this paper, a complementary metal oxide semiconductor (CMOS) frequency doubler for wireless applications at Ka-band is presented. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90 nm silicon on insulator (SOI) technology. All impedance matching, filter and bias elements are implemented on the chip, which has a very compact size of 0.37 mm/spl times/0.27 mm. At an output frequency of 27 GHz, source/load impedances of 50 /spl Omega/, a supply voltage of 1.25 V, a supply current of 8 mA and an input power of -4.5 dBm, a conversion gain of 1.5 dB was measured. To the knowledge of the authors, the circuit has by far the highest operation frequency for a CMOS frequency multiplier reported to date and requires lower supply power than circuits using leading edge III/V and silicon germanium (SiGe) technologies.     

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.     

A LDMOS technology compatible with CMOS and passive components forintegrated RF power amplifiers

The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPA's) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 3 GHz f _T and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation     

一种应用收发一体功分器设计收发馈电网络的方法

为了实现高密度的天线集成,通常会将多个天线单元紧密排列,因此需要设计连接各个单元的收发馈电网络。应用收发一体功分器级联成收发馈电网络,收发一体功分器在设计时就采用多层结构,并考虑网络层叠的影响,可以确保发射和接收互不干扰。此外,采用通孔结构,并将电阻置于底部可以降低加工难度和成本。应用该方法设计了一种收发一体双8路的馈电网络,在工作频带内,测试的反射系数小于-22 dB,隔离度高于61 dB,各个通道间的幅度一致性小于0.2 dB,相位一致性小于2.3°。该方法可缩短设计周期,提高研发效率,而且设计的馈电网络具有高隔离和低成本等优点,可用于平板阵列天线中。     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

基于自隔离技术的可集成SOI高压功率器件新结构

SOI功率器件的高耐压和高、低压间良好的隔离效果是SOI高压功率集成电路（SOI HVIC）的两项关键技术。本文提出在埋氧层（buried oxide layer,BOX）上表面处埋N岛 (buried n-islands,BNI) 的SOI LDMOS高压功率器件新结构,该结构采用自隔离技术使SOI HPIC中高压功率器件与低压控制电路单元之间达到理想的隔离效果。此外,N岛中的施主离子和位于耗尽N岛间的空穴使BOX层的电场强度从32V/μm增加到113V/μm,同时对漂移区表面电场分布进行调制,最终使器件击穿电压（BV）显著提高。实验测得一个BNI SOI LDMOS样品的耐压为673V,并在SOI HVPIC中表现出良好的隔离特性。