频率计权网络的数字电路实现

提出一种频率计权网络的数字电路实现方案,详细阐述由滤波器设计工具生成频率计权滤波器,然后采用HDL代码生成工具将其转换成可移植、可综合的能在FPGA上实现的HDL代码,分别在软件和硬件上进行仿真验证测试的过程。结果表明,设计的频率计权网络符合计权特性及允差标准,且采用此方法设计的频率计权网络简化了电路结构,操作简单,降低了功耗、成本,节省了资源,提高了效率,能快速得出信号的频率计权值。     

On-chip signature analyser for analogue circuit testing

The authors propose a technique for on-chip analogue response compaction to implement self-test capabilities in analogue circuits. The integration function is identified as a powerful analogue compression scheme and op-amp-based implementations are proposed for both single and multiple-input analysers. Validations show that an improved fault coverage can be achieved     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

数字射频存储器模块电路设计

数字射频存储器(DRFM)经过近30年的发展,已成为大多教现代电子干扰系统的核心控制部件.介绍了数字射频存储器(DRFM)在干扰机中的应用,总结了DRFM的工作原理、实现结构、性能参数及国内外应用现状和发展趋势,特别是在DRFM的基本结构上提出加入调相处理模块的设想,可以优化干扰机,达到有效干扰的目的.     

数字射频存储器模块电路设计

数字射频存储器（DRFM）经过近30年的发展,已成为大多数现代电子干扰系统的核心控制部件。介绍了数字射频存储器（DRFM）在干扰机中的应用,总结了DRFM的工作原理、实现结构、性能参数及国内外应用现状和发展趋势。特别是在DRFM的基本结构上提出加入调相处理模块的设想,可以优化干扰机,达到有效干扰的目的。     

基于DDS模块的简易数字频率特性测试仪设计

本文基于DDS技术设计了一套简易数字频率特性测试仪.本系统由DDS模块、单片机、液晶显示屏、键盘、模数转换电路和信号调理电路组成.单片机控制DDS模块产生特定频率的正弦信号,经信号调理电路缓冲、放大后送入被测网络,再经采样保持电路调理后送人ADC采样,最终经单片机处理数据后在液晶屏上显示特性曲线并给出特征信息.经实物测试,本系统设计有人机交互友好、频率测试范围广、硬件易实现等特点,具有较高的应用价值.     

用于重频窄脉冲激光能量检测的峰值保持电路

设计一种峰值保持电路。可用于高重频、窄脉冲DPL激光的脉冲能量测量。该电路主要由电荷积分电路、低通滤波电路、峰值保持电路及时间延迟电路组成。给出典型的实验波形和测试结果。实验结果表明,电路的线性动态范围约140倍。使用该检测电路可有效降低后端A／D转换器的采样频率,减小数据量,增强电路的稳定性,降低系统成本。     

用于重频窄脉冲激光能量检测的峰值保持电路

设计一种峰值保持电路,可用于高重频、窄脉冲DPL激光的脉冲能量测量.该电路主要由电荷积分电路、低通滤波电路、峰值保持电路及时间延迟电路组成.给出典型的实验波形和测试结果.实验结果表明,电路的线性动态范围约140倍.使用该检测电路可有效降低后端A/D转换器的采样频率,减小数据量,增强电路的稳定性,降低系统成本.     

应用FPGA设计的数字波形同步发送和接收VME插件

介绍了以FPGA为设计核心的16位数字波形发送和接收插件及其工作原理.插件为6U的VME插件,可以用于电子学数据采集和控制系统及其调试.     

Wideband analyser for measurement of probability densities and distributions

A fast window comparator transforms an input random voltage to a random series of pulses with equal amplitude. For stationary processes, the d.c. component of the pulse voltage is proportional to the probability density of the input voltage. Inaccuracies due to finite switching times are considered, together with errors dependent on the nonzero window width.     

一种专用电路模块测试台的设计与使用

对于技术指标不多、形状规则的电路模块,采用常规的测试夹具和测量仪器就可以达到测试要求。但对于技术指标繁多,测试过程复杂的专用电路模块,利用常规的测试方法,工作效率低下,而且会出现因电源线的极性接反而烧坏产品的现象。因此,设计制作了专用的测试台。根据专用电路模块技术指标的要求,确定了测试台的设计方案。通过测试方法的详细说明,体现了该测试台对技术指标测试的全面性,达到了测试目的,解决了专用电路模块的生产瓶颈,大大提高了工作效率。     

An electroabsorption modulator module for digital and analogapplications

This paper presents an electroabsorption modulator (EAM) module for digital and analog (D/A) applications. Optically broad-band operation of the EAM module is studied for such digital application as wavelength division multiplexing (WDM) systems. Utilizing anisotropic electroabsorption of a multiple quantum-well (MQW) EAM, 40- and 100-nm bandwidth operations in 2.5-Gb/s digital signal transmission over 200-km standard fiber are confirmed by the experiments and the simulations, respectively. For analog applications, low distortion and high link gain characteristics of the EAM module are investigated at the wavelength of 1535 nm. High spurious-free dynamic range of 123 dB·Hz^4/5 and high link gains of -10.3 dB with matching circuit and -20.6 dB without matching circuit are obtained using the EAM module     

Alternative built-in self-test (BIST) structures for analogue circuit fault diagnosis

To increase the number of test points, while still keeping low pint overhead, an alternative built-in self-test (BIST) structure using current copiers is presented. The BIST structure allows simultaneous sampling of either voltage or current test data at various test points and shifting the data for fault diagnosis and testing.<>     

高频感应加热电源模数结合连续可调移相电路研究

为减小开关损耗和防止开关管损坏,通常要求高频感应加热设备工作在弱感性状态,为此必须在反馈回路进行相位的超前、滞后调节。传统的高频模拟移相电路存在移相角随输入信号频率变化时刻发生变化的缺点,而高频数字移相电路在移相精度要求较高时倍频难以实现。为此,文中提出了两种实用的高频模数结合移相电路实现移相角在任意需要角度范围内连续可调移相。经实验,在光伏电池片组件1 MHz高频感应焊接时满足移相要求,移相效果好。     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

High speed GaAs digital integrated circuit with clock frequency of 4.1 GHz

A maximum clock frequency of 4.1 GHz was obtained for a GaAs digital integrated circuit using deep recess normally-on GaAs MESFETs with 1.2 ?m long gate and interdigitated Schottky diodes. The Ti/Pt/Au gate electrode was made by a lift-off technique with conventional photolithography. The minimum propagation delay of a NAND/AND gate was estimated to be 100 ps/gate for a fan-out of 2 from the self-oscillation frequency of the master-slave flip-flops.     

Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.     

DC-10 GHz数字瞬时测频接收机设计

在射频前端宽开的条件下,为了实现DC-10GHz带宽范围内的信号频率瞬时测量,采用基于多速率欠采样信号处理的超宽带数字测频接收机方案设计,并运用Matlab对三个不同采样率情况下的频率求解算法进行仿真。算法仿真结果显示：当输入信号的信噪比为0dB、每个采样通道对应的FFT运算点数均为1 024时,测频精度可达±3 MHz,测频出错的概率小于3×10-5。克服了直接运用奈奎斯特采样进行DC-10GHz信号频率瞬时测量的困难。     

SET-based quantiser circuit for digital communications

A single electron transistor (SET)-based quantiser circuit has been developed for the purpose of digital communication. The proposed circuit, which consists of only two SET devices and one load capacitor, offers ultra-low power dissipation, small quantisation noise error and zero granular noise error. The proposed circuit does not require any external sampling signal for sampling the baseband signal, the sampling rate can be controlled by varying the device capacitor     

100/200Gb/s数字相干光模块的光信噪比测试

线路侧光模块CFP2-DC0在4G/5G网络建设中具有重要而广泛的应用,而光信噪比(0SNR)指标是评估其性能的重要参数.光纤通信系统中的偏振模色散(PMD)及色度色散(CD)的干扰,对0SNR性能有重要的影响,PMD及CD的干扰对系统0SNR造成的劣化即为PMD、CD的0SNR代价.探讨了0SNR的不同测试方法,并针...